[llvm] [PowerPC] Optimize allocation of Conditional Register (PR #69299)
Kai Luo via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 17 19:07:28 PDT 2023
https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/69299
>From a3a0cf0813b1429c2f5150feba1e1807edaa9acc Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Tue, 17 Oct 2023 08:18:24 +0000
Subject: [PATCH 1/3] Adjust CR allocation
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 57 +++++++++++++++++++--
1 file changed, 52 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7d913a77cc71550..28d9d09353a6382 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -565,6 +565,8 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo *MRI = &MF.getRegInfo();
+ const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
+ const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
// Call the base implementation first to set any hints based on the usual
// heuristics and decide what the return value should be. We want to return
@@ -582,15 +584,20 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
if (MF.getSubtarget<PPCSubtarget>().isISAFuture())
return BaseImplRetVal;
- // We are interested in instructions that copy values to ACC/UACC.
- // The copy into UACC will be simply a COPY to a subreg so we
- // want to allocate the corresponding physical subreg for the source.
- // The copy into ACC will be a BUILD_UACC so we want to allocate
- // the same number UACC for the source.
+ MachineBasicBlock *LastUseMBB = nullptr;
+ bool UseInOneMBB = true;
const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg);
for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) {
+ if (LastUseMBB && Use.getParent() != LastUseMBB)
+ UseInOneMBB = false;
+ LastUseMBB = Use.getParent();
const MachineOperand *ResultOp = nullptr;
Register ResultReg;
+ // We are interested in instructions that copy values to ACC/UACC.
+ // The copy into UACC will be simply a COPY to a subreg so we
+ // want to allocate the corresponding physical subreg for the source.
+ // The copy into ACC will be a BUILD_UACC so we want to allocate
+ // the same number UACC for the source.
switch (Use.getOpcode()) {
case TargetOpcode::COPY: {
ResultOp = &Use.getOperand(0);
@@ -628,6 +635,46 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
}
}
}
+
+ // In single MBB, allocate different CRs for different definitions can improve
+ // performance.
+ if (UseInOneMBB && LastUseMBB &&
+ (RegClass->hasSuperClassEq(&PPC::CRRCRegClass) ||
+ RegClass->hasSuperClassEq(&PPC::CRBITRCRegClass))) {
+ std::set<MCPhysReg> ModifiedRegisters;
+ bool Skip = true;
+ // Scan from the last instruction writes VirtReg to the beginning of the
+ // MBB.
+ for (MachineInstr &MI :
+ llvm::make_range(LastUseMBB->rbegin(), LastUseMBB->rend())) {
+ if (MI.isDebugInstr())
+ continue;
+ if (MI.modifiesRegister(VirtReg, TRI))
+ Skip = false;
+ if (Skip)
+ continue;
+ for (MachineOperand &MO : MI.operands()) {
+ if (!MO.isReg() || !MO.getReg() || !MO.getReg().isVirtual() ||
+ !MO.isDef())
+ continue;
+ MCPhysReg PhysReg = VRM->getPhys(MO.getReg());
+ if (PhysReg == VirtRegMap::NO_PHYS_REG)
+ continue;
+ llvm::copy_if(
+ TRI->superregs_inclusive(PhysReg),
+ std::inserter(ModifiedRegisters, ModifiedRegisters.begin()),
+ [&](MCPhysReg SR) { return PPC::CRRCRegClass.contains(SR); });
+ }
+ }
+ llvm::copy_if(llvm::make_range(Order.begin(), Order.end()),
+ std::back_inserter(Hints), [&](MCPhysReg Reg) {
+ return llvm::all_of(TRI->superregs_inclusive(Reg),
+ [&](MCPhysReg SR) {
+ return !ModifiedRegisters.count(SR);
+ });
+ });
+ }
+
return BaseImplRetVal;
}
>From e2891ff0d15f08e1fadd3dedc5cfb2ea7f84b2ea Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Tue, 17 Oct 2023 09:57:44 +0000
Subject: [PATCH 2/3] Minor
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 28d9d09353a6382..3c27e82fb6cb9fb 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -655,11 +655,9 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
continue;
for (MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.getReg() || !MO.getReg().isVirtual() ||
- !MO.isDef())
+ !MO.isDef() || !VRM->hasPhys(MO.getReg()))
continue;
MCPhysReg PhysReg = VRM->getPhys(MO.getReg());
- if (PhysReg == VirtRegMap::NO_PHYS_REG)
- continue;
llvm::copy_if(
TRI->superregs_inclusive(PhysReg),
std::inserter(ModifiedRegisters, ModifiedRegisters.begin()),
@@ -668,6 +666,10 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
}
llvm::copy_if(llvm::make_range(Order.begin(), Order.end()),
std::back_inserter(Hints), [&](MCPhysReg Reg) {
+ // if (TRI->regsOverlap(Reg, PPC::CR2) ||
+ // TRI->regsOverlap(Reg, PPC::CR3) ||
+ // TRI->regsOverlap(Reg, PPC::CR4))
+ // return false;
return llvm::all_of(TRI->superregs_inclusive(Reg),
[&](MCPhysReg SR) {
return !ModifiedRegisters.count(SR);
>From 9d238b9da570cc075721515eaa404ccde74f11f8 Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Wed, 18 Oct 2023 02:07:13 +0000
Subject: [PATCH 3/3] Update test checks
---
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 9 +-
.../CodeGen/PowerPC/2008-10-28-f128-i32.ll | 16 +-
llvm/test/CodeGen/PowerPC/all-atomics.ll | 16 +-
.../PowerPC/builtins-ppc-xlcompat-compare.ll | 22 +-
llvm/test/CodeGen/PowerPC/common-chain.ll | 4 +-
llvm/test/CodeGen/PowerPC/crbit-asm.ll | 117 +-
llvm/test/CodeGen/PowerPC/crbits.ll | 96 +-
.../CodeGen/PowerPC/fp-strict-conv-f128.ll | 20 +-
.../CodeGen/PowerPC/fp-strict-fcmp-spe.ll | 48 +-
llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll | 528 +++----
llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll | 8 +-
llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll | 4 +-
llvm/test/CodeGen/PowerPC/is_fpclass.ll | 12 +-
llvm/test/CodeGen/PowerPC/p10-spill-creq.ll | 12 +-
.../CodeGen/PowerPC/ppc32-selectcc-i64.ll | 6 +-
llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll | 64 +-
llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll | 4 +-
.../ppcf128-constrained-fp-intrinsics.ll | 20 +-
llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir | 4 +-
llvm/test/CodeGen/PowerPC/pr48388.ll | 4 +-
llvm/test/CodeGen/PowerPC/pr49509.ll | 4 +-
llvm/test/CodeGen/PowerPC/prefer-dqform.ll | 8 +-
llvm/test/CodeGen/PowerPC/pzero-fp-xored.ll | 8 +-
llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll | 12 +-
llvm/test/CodeGen/PowerPC/select.ll | 6 +-
llvm/test/CodeGen/PowerPC/sms-cpy-1.ll | 4 +-
llvm/test/CodeGen/PowerPC/smulfixsat.ll | 4 +-
llvm/test/CodeGen/PowerPC/spe.ll | 12 +-
.../PowerPC/stack-restore-with-setjmp.ll | 14 +-
.../umulo-128-legalisation-lowering.ll | 24 +-
.../PowerPC/urem-seteq-illegal-types.ll | 6 +-
llvm/test/CodeGen/PowerPC/vec-min-max.ll | 14 +-
llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll | 16 +-
.../PowerPC/vector-popcnt-128-ult-ugt.ll | 1220 ++++++++---------
llvm/test/CodeGen/PowerPC/vsx.ll | 8 +-
35 files changed, 1214 insertions(+), 1160 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 3c27e82fb6cb9fb..7676ded1a1cd33d 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -666,10 +666,11 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
}
llvm::copy_if(llvm::make_range(Order.begin(), Order.end()),
std::back_inserter(Hints), [&](MCPhysReg Reg) {
- // if (TRI->regsOverlap(Reg, PPC::CR2) ||
- // TRI->regsOverlap(Reg, PPC::CR3) ||
- // TRI->regsOverlap(Reg, PPC::CR4))
- // return false;
+ // Be conservative not to use callee saved CRs.
+ if (TRI->regsOverlap(Reg, PPC::CR2) ||
+ TRI->regsOverlap(Reg, PPC::CR3) ||
+ TRI->regsOverlap(Reg, PPC::CR4))
+ return false;
return llvm::all_of(TRI->superregs_inclusive(Reg),
[&](MCPhysReg SR) {
return !ModifiedRegisters.count(SR);
diff --git a/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll b/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
index 0405b25e7fb0328..08c3247ab5391c8 100644
--- a/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
+++ b/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
@@ -25,14 +25,14 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: fcmpu 1, 1, 27
; CHECK-NEXT: lwz 3, 384(1)
; CHECK-NEXT: crand 20, 6, 0
-; CHECK-NEXT: cror 20, 4, 20
+; CHECK-NEXT: cror 24, 4, 20
; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
; CHECK-NEXT: stw 4, 404(1)
; CHECK-NEXT: stw 3, 400(1)
-; CHECK-NEXT: bc 4, 20, .LBB0_2
+; CHECK-NEXT: bc 4, 24, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, 0
@@ -106,9 +106,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: fcmpu 1, 29, 0
; CHECK-NEXT: lwz 4, 156(1)
; CHECK-NEXT: crandc 20, 6, 0
-; CHECK-NEXT: cror 20, 5, 20
+; CHECK-NEXT: cror 24, 5, 20
; CHECK-NEXT: addis 3, 3, -32768
-; CHECK-NEXT: bc 12, 20, .LBB0_4
+; CHECK-NEXT: bc 12, 24, .LBB0_4
; CHECK-NEXT: # %bb.3: # %bb1
; CHECK-NEXT: ori 30, 4, 0
; CHECK-NEXT: b .LBB0_5
@@ -230,9 +230,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: fcmpu 1, 31, 0
; CHECK-NEXT: lwz 4, 28(1)
; CHECK-NEXT: crandc 20, 6, 1
-; CHECK-NEXT: cror 20, 4, 20
+; CHECK-NEXT: cror 24, 4, 20
; CHECK-NEXT: addis 3, 3, -32768
-; CHECK-NEXT: bc 12, 20, .LBB0_13
+; CHECK-NEXT: bc 12, 24, .LBB0_13
; CHECK-NEXT: # %bb.12: # %bb2
; CHECK-NEXT: ori 3, 4, 0
; CHECK-NEXT: b .LBB0_13
@@ -285,9 +285,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: fcmpu 1, 31, 0
; CHECK-NEXT: lwz 4, 92(1)
; CHECK-NEXT: crandc 20, 6, 0
-; CHECK-NEXT: cror 20, 5, 20
+; CHECK-NEXT: cror 24, 5, 20
; CHECK-NEXT: addis 3, 3, -32768
-; CHECK-NEXT: bc 12, 20, .LBB0_15
+; CHECK-NEXT: bc 12, 24, .LBB0_15
; CHECK-NEXT: b .LBB0_16
; CHECK-NEXT: .LBB0_15: # %bb3
; CHECK-NEXT: addi 4, 3, 0
diff --git a/llvm/test/CodeGen/PowerPC/all-atomics.ll b/llvm/test/CodeGen/PowerPC/all-atomics.ll
index 093253bf8f6915f..5f1adcc0a7c95aa 100644
--- a/llvm/test/CodeGen/PowerPC/all-atomics.ll
+++ b/llvm/test/CodeGen/PowerPC/all-atomics.ll
@@ -5687,14 +5687,14 @@ define dso_local i64 @atommax8(ptr nocapture noundef %ptr, i64 noundef %val) loc
; AIX32-NEXT: cmplw 5, 30
; AIX32-NEXT: cmpw 1, 5, 30
; AIX32-NEXT: li 7, 5
-; AIX32-NEXT: li 8, 5
+; AIX32-NEXT: cmplw 6, 4, 31
; AIX32-NEXT: stw 5, 56(1)
; AIX32-NEXT: mr 3, 29
; AIX32-NEXT: crandc 20, 5, 2
-; AIX32-NEXT: cmplw 1, 4, 31
-; AIX32-NEXT: crand 21, 2, 5
+; AIX32-NEXT: crand 28, 2, 25
+; AIX32-NEXT: li 8, 5
; AIX32-NEXT: stw 4, 60(1)
-; AIX32-NEXT: cror 20, 21, 20
+; AIX32-NEXT: cror 20, 28, 20
; AIX32-NEXT: isel 5, 5, 30, 20
; AIX32-NEXT: isel 6, 4, 31, 20
; AIX32-NEXT: mr 4, 28
@@ -5708,15 +5708,15 @@ define dso_local i64 @atommax8(ptr nocapture noundef %ptr, i64 noundef %val) loc
; AIX32-NEXT: cmplw 5, 30
; AIX32-NEXT: cmpw 1, 5, 30
; AIX32-NEXT: li 3, 55
+; AIX32-NEXT: cmplw 6, 4, 31
+; AIX32-NEXT: lwz 31, 76(1) # 4-byte Folded Reload
; AIX32-NEXT: lwz 30, 72(1) # 4-byte Folded Reload
; AIX32-NEXT: lwz 29, 68(1) # 4-byte Folded Reload
; AIX32-NEXT: lwz 28, 64(1) # 4-byte Folded Reload
; AIX32-NEXT: crandc 20, 5, 2
-; AIX32-NEXT: cmplw 1, 4, 31
+; AIX32-NEXT: crand 28, 2, 25
; AIX32-NEXT: li 4, 66
-; AIX32-NEXT: lwz 31, 76(1) # 4-byte Folded Reload
-; AIX32-NEXT: crand 21, 2, 5
-; AIX32-NEXT: cror 20, 21, 20
+; AIX32-NEXT: cror 20, 28, 20
; AIX32-NEXT: isel 4, 4, 3, 20
; AIX32-NEXT: li 3, 0
; AIX32-NEXT: addi 1, 1, 80
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
index aeb5e8698d71112..cf43eefb75193a1 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
@@ -9,24 +9,24 @@
; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
define dso_local signext i32 @test_builtin_ppc_cmprb(i32 %a, i32%b, i32 %c, i32%d) {
-; CHECK-32-LABEL: test_builtin_ppc_cmprb:
-; CHECK-32: # %bb.0: # %entry
-; CHECK-32-NEXT: cmprb 0, 0, 3, 4
-; CHECK-32-NEXT: setb 3, 0
-; CHECK-32-NEXT: cmprb 0, 1, 5, 6
-; CHECK-32-NEXT: setb 4, 0
-; CHECK-32-NEXT: add 3, 3, 4
-; CHECK-32-NEXT: blr
-;
; CHECK-64-LABEL: test_builtin_ppc_cmprb:
; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: cmprb 0, 0, 3, 4
+; CHECK-64-NEXT: cmprb 1, 1, 5, 6
; CHECK-64-NEXT: setb 3, 0
-; CHECK-64-NEXT: cmprb 0, 1, 5, 6
-; CHECK-64-NEXT: setb 4, 0
+; CHECK-64-NEXT: setb 4, 1
; CHECK-64-NEXT: add 3, 3, 4
; CHECK-64-NEXT: extsw 3, 3
; CHECK-64-NEXT: blr
+;
+; CHECK-32-LABEL: test_builtin_ppc_cmprb:
+; CHECK-32: # %bb.0: # %entry
+; CHECK-32-NEXT: cmprb 0, 0, 3, 4
+; CHECK-32-NEXT: cmprb 1, 1, 5, 6
+; CHECK-32-NEXT: setb 3, 0
+; CHECK-32-NEXT: setb 4, 1
+; CHECK-32-NEXT: add 3, 3, 4
+; CHECK-32-NEXT: blr
entry:
%0 = call i32 @llvm.ppc.cmprb(i32 0, i32 %a, i32 %b)
%1 = call i32 @llvm.ppc.cmprb(i32 1, i32 %c, i32 %d)
diff --git a/llvm/test/CodeGen/PowerPC/common-chain.ll b/llvm/test/CodeGen/PowerPC/common-chain.ll
index 5f8c21e30f8fd06..6bbb96afa472546 100644
--- a/llvm/test/CodeGen/PowerPC/common-chain.ll
+++ b/llvm/test/CodeGen/PowerPC/common-chain.ll
@@ -753,8 +753,8 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
; CHECK-NEXT: iselgt r7, r6, r7
; CHECK-NEXT: addi r8, r7, -1
; CHECK-NEXT: clrldi r6, r7, 63
-; CHECK-NEXT: cmpldi r8, 3
-; CHECK-NEXT: blt cr0, .LBB7_4
+; CHECK-NEXT: cmpldi cr1, r8, 3
+; CHECK-NEXT: blt cr1, .LBB7_4
; CHECK-NEXT: # %bb.2: # %for.body.preheader.new
; CHECK-NEXT: ld r14, -168(r1) # 8-byte Folded Reload
; CHECK-NEXT: mulli r24, r30, 24
diff --git a/llvm/test/CodeGen/PowerPC/crbit-asm.ll b/llvm/test/CodeGen/PowerPC/crbit-asm.ll
index ffd8cb10f830d5e..3255a39f99fbec8 100644
--- a/llvm/test/CodeGen/PowerPC/crbit-asm.ll
+++ b/llvm/test/CodeGen/PowerPC/crbit-asm.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
@@ -7,29 +8,71 @@ target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
+; CHECK-LABEL: testi1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi. 3, 3, 1
+; CHECK-NEXT: crmove 20, 1
+; CHECK-NEXT: andi. 3, 4, 1
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, 1
+; CHECK-NEXT: #APP
+; CHECK-NEXT: crand 24, 20, 1
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: isel 3, 4, 3, 24
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi1:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
+; CHECK-NO-ISEL-NEXT: crmove 20, 1
+; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
+; CHECK-NO-ISEL-NEXT: li 3, 0
+; CHECK-NO-ISEL-NEXT: li 4, 1
+; CHECK-NO-ISEL-NEXT: #APP
+; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
+; CHECK-NO-ISEL-NEXT: #NO_APP
+; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB0_1
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB0_1: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
%1 = and i8 %0, 1
%tobool3 = icmp ne i8 %1, 0
ret i1 %tobool3
-; CHECK-LABEL: @testi1
-; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
-; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
-; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
-; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], 1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
-; CHECK-NO-ISEL-LABEL: @testi1
-; CHECK-NO-ISEL: bc 12, 20,
-; CHECK-NO-ISEL: blr
-; CHECK-NO-ISEL: addi 3, 4, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
+; CHECK-LABEL: testi32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi. 3, 3, 1
+; CHECK-NEXT: crmove 20, 1
+; CHECK-NEXT: andi. 3, 4, 1
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, -1
+; CHECK-NEXT: #APP
+; CHECK-NEXT: crand 24, 20, 1
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: isel 3, 4, 3, 24
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
+; CHECK-NO-ISEL-NEXT: crmove 20, 1
+; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
+; CHECK-NO-ISEL-NEXT: li 3, 0
+; CHECK-NO-ISEL-NEXT: li 4, -1
+; CHECK-NO-ISEL-NEXT: #APP
+; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
+; CHECK-NO-ISEL-NEXT: #NO_APP
+; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB1_1
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB1_1: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0
ret i32 %0
@@ -37,31 +80,41 @@ entry:
; The ABI sign_extend should combine with the any_extend from the asm result,
; and the result will be 0 or -1. This highlights the fact that only the first
; bit is meaningful.
-; CHECK-LABEL: @testi32
-; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
-; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
-; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
-; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], -1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
-; CHECK: blr
}
define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
+; CHECK-LABEL: testi8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi. 3, 3, 1
+; CHECK-NEXT: crmove 20, 1
+; CHECK-NEXT: andi. 3, 4, 1
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, 1
+; CHECK-NEXT: #APP
+; CHECK-NEXT: crand 24, 20, 1
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: isel 3, 4, 3, 24
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi8:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
+; CHECK-NO-ISEL-NEXT: crmove 20, 1
+; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
+; CHECK-NO-ISEL-NEXT: li 3, 0
+; CHECK-NO-ISEL-NEXT: li 4, 1
+; CHECK-NO-ISEL-NEXT: #APP
+; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
+; CHECK-NO-ISEL-NEXT: #NO_APP
+; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB2_1
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB2_1: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0
ret i8 %0
-; CHECK-LABEL: @testi8
-; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
-; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
-; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
-; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], 1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
-; CHECK: blr
}
attributes #0 = { nounwind "target-features"="+crbits" }
diff --git a/llvm/test/CodeGen/PowerPC/crbits.ll b/llvm/test/CodeGen/PowerPC/crbits.ll
index a682f69a2ceb781..2fc1c1dfcac8ce2 100644
--- a/llvm/test/CodeGen/PowerPC/crbits.ll
+++ b/llvm/test/CodeGen/PowerPC/crbits.ll
@@ -15,27 +15,27 @@
define zeroext i1 @test1(float %v1, float %v2) #0 {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fcmpu 0, 1, 2
; CHECK-NEXT: xxlxor 0, 0, 0
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: fcmpu 6, 2, 2
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: fcmpu 1, 2, 2
+; CHECK-NEXT: fcmpu 1, 2, 0
; CHECK-NEXT: crnor 20, 3, 0
-; CHECK-NEXT: fcmpu 0, 2, 0
-; CHECK-NEXT: crnor 21, 7, 1
-; CHECK-NEXT: crnand 20, 20, 21
+; CHECK-NEXT: crnor 28, 27, 5
+; CHECK-NEXT: crnand 20, 20, 28
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: test1:
; CHECK-NO-ISEL: # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
; CHECK-NO-ISEL-NEXT: xxlxor 0, 0, 0
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: fcmpu 6, 2, 2
; CHECK-NO-ISEL-NEXT: li 3, 1
-; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 2
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 0
; CHECK-NO-ISEL-NEXT: crnor 20, 3, 0
-; CHECK-NO-ISEL-NEXT: fcmpu 0, 2, 0
-; CHECK-NO-ISEL-NEXT: crnor 21, 7, 1
-; CHECK-NO-ISEL-NEXT: crnand 20, 20, 21
+; CHECK-NO-ISEL-NEXT: crnor 28, 27, 5
+; CHECK-NO-ISEL-NEXT: crnand 20, 20, 28
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_1
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: .LBB0_1: # %entry
@@ -44,13 +44,13 @@ define zeroext i1 @test1(float %v1, float %v2) #0 {
;
; CHECK-P10-LABEL: test1:
; CHECK-P10: # %bb.0: # %entry
-; CHECK-P10-NEXT: fcmpu cr0, f1, f2
; CHECK-P10-NEXT: xxlxor f0, f0, f0
-; CHECK-P10-NEXT: fcmpu cr1, f2, f2
+; CHECK-P10-NEXT: fcmpu cr0, f1, f2
+; CHECK-P10-NEXT: fcmpu cr6, f2, f2
+; CHECK-P10-NEXT: fcmpu cr1, f2, f0
; CHECK-P10-NEXT: crnor 4*cr5+lt, un, lt
-; CHECK-P10-NEXT: fcmpu cr0, f2, f0
-; CHECK-P10-NEXT: crnor 4*cr5+gt, 4*cr1+un, gt
-; CHECK-P10-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-P10-NEXT: crnor 4*cr7+lt, 4*cr6+un, 4*cr1+gt
+; CHECK-P10-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr7+lt
; CHECK-P10-NEXT: setbc r3, 4*cr5+lt
; CHECK-P10-NEXT: blr
entry:
@@ -66,27 +66,27 @@ entry:
define zeroext i1 @test2(float %v1, float %v2) #0 {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fcmpu 0, 1, 2
; CHECK-NEXT: xxlxor 0, 0, 0
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: fcmpu 6, 2, 2
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: fcmpu 1, 2, 2
+; CHECK-NEXT: fcmpu 1, 2, 0
; CHECK-NEXT: crnor 20, 3, 0
-; CHECK-NEXT: fcmpu 0, 2, 0
-; CHECK-NEXT: crnor 21, 7, 1
-; CHECK-NEXT: creqv 20, 20, 21
+; CHECK-NEXT: crnor 28, 27, 5
+; CHECK-NEXT: creqv 20, 20, 28
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: test2:
; CHECK-NO-ISEL: # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
; CHECK-NO-ISEL-NEXT: xxlxor 0, 0, 0
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: fcmpu 6, 2, 2
; CHECK-NO-ISEL-NEXT: li 3, 1
-; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 2
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 0
; CHECK-NO-ISEL-NEXT: crnor 20, 3, 0
-; CHECK-NO-ISEL-NEXT: fcmpu 0, 2, 0
-; CHECK-NO-ISEL-NEXT: crnor 21, 7, 1
-; CHECK-NO-ISEL-NEXT: creqv 20, 20, 21
+; CHECK-NO-ISEL-NEXT: crnor 28, 27, 5
+; CHECK-NO-ISEL-NEXT: creqv 20, 20, 28
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_1
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: .LBB1_1: # %entry
@@ -95,13 +95,13 @@ define zeroext i1 @test2(float %v1, float %v2) #0 {
;
; CHECK-P10-LABEL: test2:
; CHECK-P10: # %bb.0: # %entry
-; CHECK-P10-NEXT: fcmpu cr0, f1, f2
; CHECK-P10-NEXT: xxlxor f0, f0, f0
-; CHECK-P10-NEXT: fcmpu cr1, f2, f2
+; CHECK-P10-NEXT: fcmpu cr0, f1, f2
+; CHECK-P10-NEXT: fcmpu cr6, f2, f2
+; CHECK-P10-NEXT: fcmpu cr1, f2, f0
; CHECK-P10-NEXT: crnor 4*cr5+lt, un, lt
-; CHECK-P10-NEXT: fcmpu cr0, f2, f0
-; CHECK-P10-NEXT: crnor 4*cr5+gt, 4*cr1+un, gt
-; CHECK-P10-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-P10-NEXT: crnor 4*cr7+lt, 4*cr6+un, 4*cr1+gt
+; CHECK-P10-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr7+lt
; CHECK-P10-NEXT: setbc r3, 4*cr5+lt
; CHECK-P10-NEXT: blr
entry:
@@ -117,30 +117,30 @@ entry:
define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fcmpu 0, 1, 2
; CHECK-NEXT: xxlxor 0, 0, 0
+; CHECK-NEXT: fcmpu 6, 2, 2
+; CHECK-NEXT: fcmpu 0, 1, 2
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: fcmpu 1, 2, 2
+; CHECK-NEXT: fcmpu 1, 2, 0
; CHECK-NEXT: crnor 20, 3, 0
-; CHECK-NEXT: fcmpu 0, 2, 0
-; CHECK-NEXT: crnor 21, 7, 1
; CHECK-NEXT: cmpwi 5, -2
-; CHECK-NEXT: crandc 21, 21, 2
+; CHECK-NEXT: crnor 28, 27, 5
+; CHECK-NEXT: crandc 21, 28, 2
; CHECK-NEXT: creqv 20, 20, 21
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: test3:
; CHECK-NO-ISEL: # %bb.0: # %entry
-; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
; CHECK-NO-ISEL-NEXT: xxlxor 0, 0, 0
+; CHECK-NO-ISEL-NEXT: fcmpu 6, 2, 2
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
; CHECK-NO-ISEL-NEXT: li 3, 1
-; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 2
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 0
; CHECK-NO-ISEL-NEXT: crnor 20, 3, 0
-; CHECK-NO-ISEL-NEXT: fcmpu 0, 2, 0
-; CHECK-NO-ISEL-NEXT: crnor 21, 7, 1
; CHECK-NO-ISEL-NEXT: cmpwi 5, -2
-; CHECK-NO-ISEL-NEXT: crandc 21, 21, 2
+; CHECK-NO-ISEL-NEXT: crnor 28, 27, 5
+; CHECK-NO-ISEL-NEXT: crandc 21, 28, 2
; CHECK-NO-ISEL-NEXT: creqv 20, 20, 21
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_1
; CHECK-NO-ISEL-NEXT: blr
@@ -150,14 +150,14 @@ define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
;
; CHECK-P10-LABEL: test3:
; CHECK-P10: # %bb.0: # %entry
-; CHECK-P10-NEXT: fcmpu cr0, f1, f2
; CHECK-P10-NEXT: xxlxor f0, f0, f0
-; CHECK-P10-NEXT: fcmpu cr1, f2, f2
+; CHECK-P10-NEXT: fcmpu cr0, f1, f2
+; CHECK-P10-NEXT: fcmpu cr6, f2, f2
+; CHECK-P10-NEXT: fcmpu cr1, f2, f0
; CHECK-P10-NEXT: crnor 4*cr5+lt, un, lt
-; CHECK-P10-NEXT: fcmpu cr0, f2, f0
-; CHECK-P10-NEXT: crnor 4*cr5+gt, 4*cr1+un, gt
; CHECK-P10-NEXT: cmpwi r5, -2
-; CHECK-P10-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
+; CHECK-P10-NEXT: crnor 4*cr7+lt, 4*cr6+un, 4*cr1+gt
+; CHECK-P10-NEXT: crandc 4*cr5+gt, 4*cr7+lt, eq
; CHECK-P10-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
; CHECK-P10-NEXT: setbc r3, 4*cr5+lt
; CHECK-P10-NEXT: blr
@@ -275,9 +275,9 @@ define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
; CHECK-P10-NEXT: cmpwi cr1, r5, -2
; CHECK-P10-NEXT: crmove 4*cr5+lt, gt
; CHECK-P10-NEXT: andi. r3, r4, 1
-; CHECK-P10-NEXT: crorc 4*cr5+gt, gt, 4*cr1+eq
-; CHECK-P10-NEXT: crand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; CHECK-P10-NEXT: setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT: crorc 4*cr6+lt, gt, 4*cr1+eq
+; CHECK-P10-NEXT: crand 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; CHECK-P10-NEXT: setbc r3, 4*cr7+lt
; CHECK-P10-NEXT: blr
entry:
%cmp = icmp ne i32 %v3, -2
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
index 988ec6d8cc72bf2..1d667c61450d5f8 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
@@ -620,10 +620,10 @@ define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 {
; P8-NEXT: lis r3, -32768
; P8-NEXT: fcmpo cr0, f1, f0
; P8-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; P8-NEXT: crandc 4*cr5+gt, lt, eq
-; P8-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r30, 0, r3, 4*cr5+lt
-; P8-NEXT: bc 12, 4*cr5+lt, .LBB13_2
+; P8-NEXT: crandc 4*cr6+lt, lt, eq
+; P8-NEXT: cror 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r30, 0, r3, 4*cr7+lt
+; P8-NEXT: bc 12, 4*cr7+lt, .LBB13_2
; P8-NEXT: # %bb.1: # %entry
; P8-NEXT: fmr f3, f0
; P8-NEXT: .LBB13_2: # %entry
@@ -661,10 +661,10 @@ define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 {
; P9-NEXT: lis r3, -32768
; P9-NEXT: fcmpo cr0, f1, f0
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; P9-NEXT: crandc 4*cr5+gt, lt, eq
-; P9-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r30, 0, r3, 4*cr5+lt
-; P9-NEXT: bc 12, 4*cr5+lt, .LBB13_2
+; P9-NEXT: crandc 4*cr6+lt, lt, eq
+; P9-NEXT: cror 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r30, 0, r3, 4*cr7+lt
+; P9-NEXT: bc 12, 4*cr7+lt, .LBB13_2
; P9-NEXT: # %bb.1: # %entry
; P9-NEXT: fmr f3, f0
; P9-NEXT: .LBB13_2: # %entry
@@ -703,9 +703,9 @@ define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 {
; NOVSX-NEXT: fcmpo cr0, f1, f0
; NOVSX-NEXT: fcmpo cr1, f2, f4
; NOVSX-NEXT: fmr f3, f4
-; NOVSX-NEXT: crandc 4*cr5+gt, lt, eq
+; NOVSX-NEXT: crandc 4*cr6+lt, lt, eq
; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; NOVSX-NEXT: cror 4*cr2+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: cror 4*cr2+lt, 4*cr6+lt, 4*cr5+lt
; NOVSX-NEXT: bc 12, 4*cr2+lt, .LBB13_2
; NOVSX-NEXT: # %bb.1: # %entry
; NOVSX-NEXT: fmr f3, f0
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
index 6aae299786cc7e9..02a861611573e3c 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
@@ -33,9 +33,9 @@ define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-NEXT: efscmpeq cr0, r6, r6
; SPE-NEXT: efscmpeq cr1, r5, r5
; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: crandc 4*cr5+lt, 4*cr5+lt, gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
+; SPE-NEXT: efscmplt cr6, r5, r6
+; SPE-NEXT: crandc 4*cr7+lt, 4*cr5+lt, 4*cr6+gt
+; SPE-NEXT: bclr 12, 4*cr7+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
; SPE-NEXT: blr
@@ -63,9 +63,9 @@ define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-NEXT: efscmpeq cr0, r6, r6
; SPE-NEXT: efscmpeq cr1, r5, r5
; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: crandc 4*cr5+lt, 4*cr5+lt, gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
+; SPE-NEXT: efscmpgt cr6, r5, r6
+; SPE-NEXT: crandc 4*cr7+lt, 4*cr5+lt, 4*cr6+gt
+; SPE-NEXT: bclr 12, 4*cr7+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
; SPE-NEXT: blr
@@ -126,9 +126,9 @@ define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-NEXT: efscmpeq cr0, r5, r5
; SPE-NEXT: efscmpeq cr1, r6, r6
; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: cror 4*cr5+lt, gt, 4*cr5+lt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
+; SPE-NEXT: efscmpgt cr6, r5, r6
+; SPE-NEXT: cror 4*cr7+lt, 4*cr6+gt, 4*cr5+lt
+; SPE-NEXT: bclr 12, 4*cr7+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
; SPE-NEXT: blr
@@ -157,9 +157,9 @@ define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-NEXT: efscmpeq cr0, r5, r5
; SPE-NEXT: efscmpeq cr1, r6, r6
; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: cror 4*cr5+lt, gt, 4*cr5+lt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
+; SPE-NEXT: efscmplt cr6, r5, r6
+; SPE-NEXT: cror 4*cr7+lt, 4*cr6+gt, 4*cr5+lt
+; SPE-NEXT: bclr 12, 4*cr7+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
; SPE-NEXT: blr
@@ -249,9 +249,9 @@ define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: efdcmpeq cr0, r6, r6
; SPE-NEXT: efdcmpeq cr1, r5, r5
; SPE-NEXT: efdcmplt cr5, r5, r6
-; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
-; SPE-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
+; SPE-NEXT: crand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT: crandc 4*cr7+lt, 4*cr6+lt, 4*cr5+gt
+; SPE-NEXT: bclr 12, 4*cr7+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
; SPE-NEXT: blr
@@ -283,9 +283,9 @@ define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: efdcmpeq cr0, r6, r6
; SPE-NEXT: efdcmpeq cr1, r5, r5
; SPE-NEXT: efdcmpgt cr5, r5, r6
-; SPE-NEXT: crand 4*cr5+lt, 4*cr1+gt, gt
-; SPE-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
+; SPE-NEXT: crand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT: crandc 4*cr7+lt, 4*cr6+lt, 4*cr5+gt
+; SPE-NEXT: bclr 12, 4*cr7+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
; SPE-NEXT: blr
@@ -354,9 +354,9 @@ define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: efdcmpeq cr0, r5, r5
; SPE-NEXT: efdcmpeq cr1, r7, r7
; SPE-NEXT: efdcmpgt cr5, r5, r7
-; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
+; SPE-NEXT: crnand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT: cror 4*cr7+lt, 4*cr5+gt, 4*cr6+lt
+; SPE-NEXT: bclr 12, 4*cr7+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
; SPE-NEXT: blr
@@ -389,9 +389,9 @@ define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-NEXT: efdcmpeq cr0, r5, r5
; SPE-NEXT: efdcmpeq cr1, r7, r7
; SPE-NEXT: efdcmplt cr5, r5, r7
-; SPE-NEXT: crnand 4*cr5+lt, 4*cr1+gt, gt
-; SPE-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; SPE-NEXT: bclr 12, 4*cr5+lt, 0
+; SPE-NEXT: crnand 4*cr6+lt, 4*cr1+gt, gt
+; SPE-NEXT: cror 4*cr7+lt, 4*cr5+gt, 4*cr6+lt
+; SPE-NEXT: bclr 12, 4*cr7+lt, 0
; SPE-NEXT: # %bb.1:
; SPE-NEXT: ori r3, r4, 0
; SPE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
index af4c051d553eeed..9867a460629c624 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
@@ -2660,11 +2660,11 @@ define i32 @fcmp_olt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: crandc 4*cr5+gt, lt, eq
+; P8-NEXT: crandc 4*cr6+lt, lt, eq
; P8-NEXT: fcmpu cr1, f2, f4
; P8-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_olt_ppcf128:
@@ -2673,20 +2673,20 @@ define i32 @fcmp_olt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; P9-NEXT: crandc 4*cr5+gt, lt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crandc 4*cr6+lt, lt, eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_olt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: crandc 4*cr5+gt, lt, eq
+; NOVSX-NEXT: crandc 4*cr6+lt, lt, eq
; NOVSX-NEXT: fcmpu cr1, f2, f4
; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -2699,24 +2699,24 @@ define i32 @fcmp_ole_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, gt
-; P8-NEXT: fcmpu cr0, f1, f3
-; P8-NEXT: crnor 4*cr5+gt, un, gt
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: fcmpu cr1, f1, f3
+; P8-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+gt
+; P8-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ole_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
+; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, un, gt
-; P9-NEXT: fcmpu cr0, f1, f3
-; P9-NEXT: crnor 4*cr5+gt, un, gt
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+gt
+; P9-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -2725,11 +2725,11 @@ define i32 @fcmp_ole_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, gt
-; NOVSX-NEXT: fcmpu cr0, f1, f3
-; NOVSX-NEXT: crnor 4*cr5+gt, un, gt
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: fcmpu cr1, f1, f3
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+gt
+; NOVSX-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0
@@ -2742,11 +2742,11 @@ define i32 @fcmp_ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: crandc 4*cr5+gt, gt, eq
+; P8-NEXT: crandc 4*cr6+lt, gt, eq
; P8-NEXT: fcmpu cr1, f2, f4
; P8-NEXT: crand 4*cr5+lt, eq, 4*cr1+gt
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ogt_ppcf128:
@@ -2755,20 +2755,20 @@ define i32 @fcmp_ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+gt
-; P9-NEXT: crandc 4*cr5+gt, gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crandc 4*cr6+lt, gt, eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_ogt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: crandc 4*cr5+gt, gt, eq
+; NOVSX-NEXT: crandc 4*cr6+lt, gt, eq
; NOVSX-NEXT: fcmpu cr1, f2, f4
; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr1+gt
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -2781,24 +2781,24 @@ define i32 @fcmp_oge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, lt
-; P8-NEXT: fcmpu cr0, f1, f3
-; P8-NEXT: crnor 4*cr5+gt, un, lt
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: fcmpu cr1, f1, f3
+; P8-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+lt
+; P8-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_oge_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
+; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, un, lt
-; P9-NEXT: fcmpu cr0, f1, f3
-; P9-NEXT: crnor 4*cr5+gt, un, lt
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+lt
+; P9-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -2807,11 +2807,11 @@ define i32 @fcmp_oge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, lt
-; NOVSX-NEXT: fcmpu cr0, f1, f3
-; NOVSX-NEXT: crnor 4*cr5+gt, un, lt
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: fcmpu cr1, f1, f3
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+lt
+; NOVSX-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
@@ -2824,11 +2824,11 @@ define i32 @fcmp_oeq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: crandc 4*cr5+gt, eq, eq
+; P8-NEXT: crandc 4*cr6+lt, eq, eq
; P8-NEXT: fcmpu cr1, f2, f4
; P8-NEXT: crand 4*cr5+lt, eq, 4*cr1+eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_oeq_ppcf128:
@@ -2837,20 +2837,20 @@ define i32 @fcmp_oeq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+eq
-; P9-NEXT: crandc 4*cr5+gt, eq, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crandc 4*cr6+lt, eq, eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_oeq_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: crandc 4*cr5+gt, eq, eq
+; NOVSX-NEXT: crandc 4*cr6+lt, eq, eq
; NOVSX-NEXT: fcmpu cr1, f2, f4
; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr1+eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -2863,24 +2863,24 @@ define i32 @fcmp_one_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: fcmpu cr0, f2, f4
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, eq
-; P8-NEXT: fcmpu cr0, f1, f3
-; P8-NEXT: crnor 4*cr5+gt, un, eq
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: fcmpu cr1, f1, f3
+; P8-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+eq
+; P8-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_one_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpu cr0, f2, f4
+; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, un, eq
-; P9-NEXT: fcmpu cr0, f1, f3
-; P9-NEXT: crnor 4*cr5+gt, un, eq
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+eq
+; P9-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -2889,11 +2889,11 @@ define i32 @fcmp_one_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: fcmpu cr0, f2, f4
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, eq
-; NOVSX-NEXT: fcmpu cr0, f1, f3
-; NOVSX-NEXT: crnor 4*cr5+gt, un, eq
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: fcmpu cr1, f1, f3
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+eq
+; NOVSX-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"one", metadata !"fpexcept.strict") #0
@@ -2906,12 +2906,12 @@ define i32 @fcmp_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: cror 4*cr5+gt, lt, un
+; P8-NEXT: cror 4*cr7+lt, lt, un
; P8-NEXT: fcmpu cr1, f2, f4
; P8-NEXT: cror 4*cr5+lt, 4*cr1+lt, 4*cr1+un
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
@@ -2921,10 +2921,10 @@ define i32 @fcmp_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, 4*cr1+lt, 4*cr1+un
-; P9-NEXT: cror 4*cr5+gt, lt, un
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr7+lt, lt, un
+; P9-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -2932,12 +2932,12 @@ define i32 @fcmp_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: cror 4*cr5+gt, lt, un
+; NOVSX-NEXT: cror 4*cr7+lt, lt, un
; NOVSX-NEXT: fcmpu cr1, f2, f4
; NOVSX-NEXT: cror 4*cr5+lt, 4*cr1+lt, 4*cr1+un
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
@@ -2952,9 +2952,9 @@ define i32 @fcmp_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: li r3, 1
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
-; P8-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr6+lt, 4*cr1+gt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_ule_ppcf128:
@@ -2963,9 +2963,9 @@ define i32 @fcmp_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
-; P9-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crnor 4*cr6+lt, 4*cr1+gt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_ule_ppcf128:
@@ -2974,9 +2974,9 @@ define i32 @fcmp_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
-; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr6+lt, 4*cr1+gt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -2988,12 +2988,12 @@ define i32 @fcmp_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: cror 4*cr5+gt, gt, un
+; P8-NEXT: cror 4*cr7+lt, gt, un
; P8-NEXT: fcmpu cr1, f2, f4
; P8-NEXT: cror 4*cr5+lt, 4*cr1+gt, 4*cr1+un
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
@@ -3003,10 +3003,10 @@ define i32 @fcmp_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, 4*cr1+gt, 4*cr1+un
-; P9-NEXT: cror 4*cr5+gt, gt, un
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr7+lt, gt, un
+; P9-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -3014,12 +3014,12 @@ define i32 @fcmp_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: cror 4*cr5+gt, gt, un
+; NOVSX-NEXT: cror 4*cr7+lt, gt, un
; NOVSX-NEXT: fcmpu cr1, f2, f4
; NOVSX-NEXT: cror 4*cr5+lt, 4*cr1+gt, 4*cr1+un
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0
@@ -3034,9 +3034,9 @@ define i32 @fcmp_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: li r3, 1
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
-; P8-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr6+lt, 4*cr1+lt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_uge_ppcf128:
@@ -3045,9 +3045,9 @@ define i32 @fcmp_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
-; P9-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crnor 4*cr6+lt, 4*cr1+lt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_uge_ppcf128:
@@ -3056,9 +3056,9 @@ define i32 @fcmp_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
-; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr6+lt, 4*cr1+lt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -3070,12 +3070,12 @@ define i32 @fcmp_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpu cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: cror 4*cr5+gt, eq, un
+; P8-NEXT: cror 4*cr7+lt, eq, un
; P8-NEXT: fcmpu cr1, f2, f4
; P8-NEXT: cror 4*cr5+lt, 4*cr1+eq, 4*cr1+un
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
@@ -3085,10 +3085,10 @@ define i32 @fcmp_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, 4*cr1+eq, 4*cr1+un
-; P9-NEXT: cror 4*cr5+gt, eq, un
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr7+lt, eq, un
+; P9-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -3096,12 +3096,12 @@ define i32 @fcmp_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpu cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: cror 4*cr5+gt, eq, un
+; NOVSX-NEXT: cror 4*cr7+lt, eq, un
; NOVSX-NEXT: fcmpu cr1, f2, f4
; NOVSX-NEXT: cror 4*cr5+lt, 4*cr1+eq, 4*cr1+un
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ueq", metadata !"fpexcept.strict") #0
@@ -3116,8 +3116,8 @@ define i32 @fcmp_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: li r3, 1
; P8-NEXT: fcmpu cr1, f1, f3
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
-; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crandc 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr6+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmp_une_ppcf128:
@@ -3126,8 +3126,8 @@ define i32 @fcmp_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpu cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
-; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crandc 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr6+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmp_une_ppcf128:
@@ -3136,8 +3136,8 @@ define i32 @fcmp_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: fcmpu cr1, f1, f3
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
-; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr6+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -3149,11 +3149,11 @@ define i32 @fcmps_olt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpo cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: crandc 4*cr5+gt, lt, eq
+; P8-NEXT: crandc 4*cr6+lt, lt, eq
; P8-NEXT: fcmpo cr1, f2, f4
; P8-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_olt_ppcf128:
@@ -3162,20 +3162,20 @@ define i32 @fcmps_olt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; P9-NEXT: crandc 4*cr5+gt, lt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crandc 4*cr6+lt, lt, eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_olt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpo cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: crandc 4*cr5+gt, lt, eq
+; NOVSX-NEXT: crandc 4*cr6+lt, lt, eq
; NOVSX-NEXT: fcmpo cr1, f2, f4
; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -3188,24 +3188,24 @@ define i32 @fcmps_ole_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: fcmpo cr0, f2, f4
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, gt
-; P8-NEXT: fcmpo cr0, f1, f3
-; P8-NEXT: crnor 4*cr5+gt, un, gt
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: fcmpo cr1, f1, f3
+; P8-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+gt
+; P8-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ole_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpo cr0, f2, f4
+; P9-NEXT: fcmpo cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, un, gt
-; P9-NEXT: fcmpo cr0, f1, f3
-; P9-NEXT: crnor 4*cr5+gt, un, gt
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+gt
+; P9-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -3214,11 +3214,11 @@ define i32 @fcmps_ole_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: fcmpo cr0, f2, f4
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, gt
-; NOVSX-NEXT: fcmpo cr0, f1, f3
-; NOVSX-NEXT: crnor 4*cr5+gt, un, gt
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: fcmpo cr1, f1, f3
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+gt
+; NOVSX-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0
@@ -3231,11 +3231,11 @@ define i32 @fcmps_ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpo cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: crandc 4*cr5+gt, gt, eq
+; P8-NEXT: crandc 4*cr6+lt, gt, eq
; P8-NEXT: fcmpo cr1, f2, f4
; P8-NEXT: crand 4*cr5+lt, eq, 4*cr1+gt
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ogt_ppcf128:
@@ -3244,20 +3244,20 @@ define i32 @fcmps_ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+gt
-; P9-NEXT: crandc 4*cr5+gt, gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crandc 4*cr6+lt, gt, eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_ogt_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpo cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: crandc 4*cr5+gt, gt, eq
+; NOVSX-NEXT: crandc 4*cr6+lt, gt, eq
; NOVSX-NEXT: fcmpo cr1, f2, f4
; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr1+gt
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -3270,24 +3270,24 @@ define i32 @fcmps_oge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: fcmpo cr0, f2, f4
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, lt
-; P8-NEXT: fcmpo cr0, f1, f3
-; P8-NEXT: crnor 4*cr5+gt, un, lt
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: fcmpo cr1, f1, f3
+; P8-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+lt
+; P8-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_oge_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpo cr0, f2, f4
+; P9-NEXT: fcmpo cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, un, lt
-; P9-NEXT: fcmpo cr0, f1, f3
-; P9-NEXT: crnor 4*cr5+gt, un, lt
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+lt
+; P9-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -3296,11 +3296,11 @@ define i32 @fcmps_oge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: fcmpo cr0, f2, f4
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, lt
-; NOVSX-NEXT: fcmpo cr0, f1, f3
-; NOVSX-NEXT: crnor 4*cr5+gt, un, lt
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: fcmpo cr1, f1, f3
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+lt
+; NOVSX-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
@@ -3313,11 +3313,11 @@ define i32 @fcmps_oeq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpo cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: crandc 4*cr5+gt, eq, eq
+; P8-NEXT: crandc 4*cr6+lt, eq, eq
; P8-NEXT: fcmpo cr1, f2, f4
; P8-NEXT: crand 4*cr5+lt, eq, 4*cr1+eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_oeq_ppcf128:
@@ -3326,20 +3326,20 @@ define i32 @fcmps_oeq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+eq
-; P9-NEXT: crandc 4*cr5+gt, eq, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crandc 4*cr6+lt, eq, eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_oeq_ppcf128:
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpo cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: crandc 4*cr5+gt, eq, eq
+; NOVSX-NEXT: crandc 4*cr6+lt, eq, eq
; NOVSX-NEXT: fcmpo cr1, f2, f4
; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr1+eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -3352,24 +3352,24 @@ define i32 @fcmps_one_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: fcmpo cr0, f2, f4
; P8-NEXT: li r3, 1
; P8-NEXT: crnor 4*cr5+lt, un, eq
-; P8-NEXT: fcmpo cr0, f1, f3
-; P8-NEXT: crnor 4*cr5+gt, un, eq
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: fcmpo cr1, f1, f3
+; P8-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+eq
+; P8-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_one_ppcf128:
; P9: # %bb.0:
; P9-NEXT: fcmpo cr0, f2, f4
+; P9-NEXT: fcmpo cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, un, eq
-; P9-NEXT: fcmpo cr0, f1, f3
-; P9-NEXT: crnor 4*cr5+gt, un, eq
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+eq
+; P9-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -3378,11 +3378,11 @@ define i32 @fcmps_one_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: fcmpo cr0, f2, f4
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: crnor 4*cr5+lt, un, eq
-; NOVSX-NEXT: fcmpo cr0, f1, f3
-; NOVSX-NEXT: crnor 4*cr5+gt, un, eq
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: fcmpo cr1, f1, f3
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr1+un, 4*cr1+eq
+; NOVSX-NEXT: crand 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"one", metadata !"fpexcept.strict") #0
@@ -3395,12 +3395,12 @@ define i32 @fcmps_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpo cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: cror 4*cr5+gt, lt, un
+; P8-NEXT: cror 4*cr7+lt, lt, un
; P8-NEXT: fcmpo cr1, f2, f4
; P8-NEXT: cror 4*cr5+lt, 4*cr1+lt, 4*cr1+un
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
@@ -3410,10 +3410,10 @@ define i32 @fcmps_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, 4*cr1+lt, 4*cr1+un
-; P9-NEXT: cror 4*cr5+gt, lt, un
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr7+lt, lt, un
+; P9-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -3421,12 +3421,12 @@ define i32 @fcmps_ult_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpo cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: cror 4*cr5+gt, lt, un
+; NOVSX-NEXT: cror 4*cr7+lt, lt, un
; NOVSX-NEXT: fcmpo cr1, f2, f4
; NOVSX-NEXT: cror 4*cr5+lt, 4*cr1+lt, 4*cr1+un
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
@@ -3441,9 +3441,9 @@ define i32 @fcmps_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: li r3, 1
; P8-NEXT: fcmpo cr1, f1, f3
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
-; P8-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr6+lt, 4*cr1+gt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_ule_ppcf128:
@@ -3452,9 +3452,9 @@ define i32 @fcmps_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
-; P9-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crnor 4*cr6+lt, 4*cr1+gt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_ule_ppcf128:
@@ -3463,9 +3463,9 @@ define i32 @fcmps_ule_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: fcmpo cr1, f1, f3
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, gt
-; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+gt, 4*cr1+eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr6+lt, 4*cr1+gt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -3477,12 +3477,12 @@ define i32 @fcmps_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpo cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: cror 4*cr5+gt, gt, un
+; P8-NEXT: cror 4*cr7+lt, gt, un
; P8-NEXT: fcmpo cr1, f2, f4
; P8-NEXT: cror 4*cr5+lt, 4*cr1+gt, 4*cr1+un
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
@@ -3492,10 +3492,10 @@ define i32 @fcmps_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, 4*cr1+gt, 4*cr1+un
-; P9-NEXT: cror 4*cr5+gt, gt, un
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr7+lt, gt, un
+; P9-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -3503,12 +3503,12 @@ define i32 @fcmps_ugt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpo cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: cror 4*cr5+gt, gt, un
+; NOVSX-NEXT: cror 4*cr7+lt, gt, un
; NOVSX-NEXT: fcmpo cr1, f2, f4
; NOVSX-NEXT: cror 4*cr5+lt, 4*cr1+gt, 4*cr1+un
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0
@@ -3523,9 +3523,9 @@ define i32 @fcmps_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: li r3, 1
; P8-NEXT: fcmpo cr1, f1, f3
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
-; P8-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crnor 4*cr6+lt, 4*cr1+lt, 4*cr1+eq
+; P8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr7+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_uge_ppcf128:
@@ -3534,9 +3534,9 @@ define i32 @fcmps_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
-; P9-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crnor 4*cr6+lt, 4*cr1+lt, 4*cr1+eq
+; P9-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr7+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_uge_ppcf128:
@@ -3545,9 +3545,9 @@ define i32 @fcmps_uge_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: fcmpo cr1, f1, f3
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, lt
-; NOVSX-NEXT: crnor 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crnor 4*cr6+lt, 4*cr1+lt, 4*cr1+eq
+; NOVSX-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr7+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
@@ -3559,12 +3559,12 @@ define i32 @fcmps_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8: # %bb.0:
; P8-NEXT: fcmpo cr0, f1, f3
; P8-NEXT: li r3, 1
-; P8-NEXT: cror 4*cr5+gt, eq, un
+; P8-NEXT: cror 4*cr7+lt, eq, un
; P8-NEXT: fcmpo cr1, f2, f4
; P8-NEXT: cror 4*cr5+lt, 4*cr1+eq, 4*cr1+un
-; P8-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P8-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P8-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P8-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P8-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
; P8-NEXT: blr
;
@@ -3574,10 +3574,10 @@ define i32 @fcmps_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f2, f4
; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, 4*cr1+eq, 4*cr1+un
-; P9-NEXT: cror 4*cr5+gt, eq, un
-; P9-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; P9-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; P9-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; P9-NEXT: cror 4*cr7+lt, eq, un
+; P9-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; P9-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; P9-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr
;
@@ -3585,12 +3585,12 @@ define i32 @fcmps_ueq_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX: # %bb.0:
; NOVSX-NEXT: fcmpo cr0, f1, f3
; NOVSX-NEXT: li r3, 1
-; NOVSX-NEXT: cror 4*cr5+gt, eq, un
+; NOVSX-NEXT: cror 4*cr7+lt, eq, un
; NOVSX-NEXT: fcmpo cr1, f2, f4
; NOVSX-NEXT: cror 4*cr5+lt, 4*cr1+eq, 4*cr1+un
-; NOVSX-NEXT: crand 4*cr5+lt, eq, 4*cr5+lt
-; NOVSX-NEXT: crandc 4*cr5+gt, 4*cr5+gt, eq
-; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; NOVSX-NEXT: crand 4*cr6+lt, eq, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr7+lt, eq
+; NOVSX-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr6+lt
; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ueq", metadata !"fpexcept.strict") #0
@@ -3605,8 +3605,8 @@ define i32 @fcmps_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P8-NEXT: li r3, 1
; P8-NEXT: fcmpo cr1, f1, f3
; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
-; P8-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
-; P8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P8-NEXT: crandc 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P8-NEXT: isel r3, 0, r3, 4*cr6+lt
; P8-NEXT: blr
;
; P9-LABEL: fcmps_une_ppcf128:
@@ -3615,8 +3615,8 @@ define i32 @fcmps_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; P9-NEXT: fcmpo cr1, f1, f3
; P9-NEXT: li r3, 1
; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
-; P9-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
-; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
+; P9-NEXT: crandc 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; P9-NEXT: isel r3, 0, r3, 4*cr6+lt
; P9-NEXT: blr
;
; NOVSX-LABEL: fcmps_une_ppcf128:
@@ -3625,8 +3625,8 @@ define i32 @fcmps_une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; NOVSX-NEXT: li r3, 1
; NOVSX-NEXT: fcmpo cr1, f1, f3
; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, eq
-; NOVSX-NEXT: crandc 4*cr5+lt, 4*cr1+eq, 4*cr5+lt
-; NOVSX-NEXT: isel r3, 0, r3, 4*cr5+lt
+; NOVSX-NEXT: crandc 4*cr6+lt, 4*cr1+eq, 4*cr5+lt
+; NOVSX-NEXT: isel r3, 0, r3, 4*cr6+lt
; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32
diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
index 9cc42cf74b7f94a..cba42ecbae5c95c 100644
--- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
@@ -106,15 +106,15 @@ define float @fooul(float %X) #0 {
; PPC64-NEXT: rldicl 5, 5, 53, 11
; PPC64-NEXT: std 4, -32(1)
; PPC64-NEXT: rldicl 4, 5, 11, 1
-; PPC64-NEXT: cmpldi 7, 1
-; PPC64-NEXT: bc 12, 1, .LBB2_6
+; PPC64-NEXT: cmpldi 1, 7, 1
+; PPC64-NEXT: bc 12, 5, .LBB2_6
; PPC64-NEXT: # %bb.5: # %entry
; PPC64-NEXT: ori 4, 6, 0
; PPC64-NEXT: b .LBB2_6
; PPC64-NEXT: .LBB2_6: # %entry
-; PPC64-NEXT: cmpdi 3, 0
+; PPC64-NEXT: cmpdi 5, 3, 0
; PPC64-NEXT: std 4, -24(1)
-; PPC64-NEXT: bc 12, 0, .LBB2_8
+; PPC64-NEXT: bc 12, 20, .LBB2_8
; PPC64-NEXT: # %bb.7: # %entry
; PPC64-NEXT: lfd 0, -32(1)
; PPC64-NEXT: fcfid 0, 0
diff --git a/llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll b/llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll
index fc93f893b1d5d66..f942798880d3044 100644
--- a/llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll
+++ b/llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll
@@ -9,6 +9,7 @@ define dso_local void @calc_buffer() local_unnamed_addr #0 {
; CHECK-NEXT: rldicl r6, r3, 63, 1
; CHECK-NEXT: clrldi r7, r3, 63
; CHECK-NEXT: clrldi r4, r3, 53
+; CHECK-NEXT: cmpdi cr5, r3, 0
; CHECK-NEXT: addi r5, r5, 1
; CHECK-NEXT: or r7, r7, r6
; CHECK-NEXT: cmpldi r5, 1
@@ -33,10 +34,9 @@ define dso_local void @calc_buffer() local_unnamed_addr #0 {
; CHECK-NEXT: ori r5, r7, 0
; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_4:
-; CHECK-NEXT: cmpdi r3, 0
; CHECK-NEXT: std r4, -32(r1)
; CHECK-NEXT: std r5, -24(r1)
-; CHECK-NEXT: bc 12, lt, .LBB0_6
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: lfd f0, -32(r1)
; CHECK-NEXT: fcfid f0, f0
diff --git a/llvm/test/CodeGen/PowerPC/is_fpclass.ll b/llvm/test/CodeGen/PowerPC/is_fpclass.ll
index 1ba4749d7437df5..587bb6cbc506ea3 100644
--- a/llvm/test/CodeGen/PowerPC/is_fpclass.ll
+++ b/llvm/test/CodeGen/PowerPC/is_fpclass.ll
@@ -425,13 +425,13 @@ define i1 @isclass_00d_double(double %x) nounwind {
; CHECK-NEXT: mffprd 3, 1
; CHECK-NEXT: xststdcdp 0, 1, 127
; CHECK-NEXT: xststdcdp 1, 1, 64
+; CHECK-NEXT: xststdcdp 7, 1, 16
; CHECK-NEXT: rldicl 3, 3, 32, 32
; CHECK-NEXT: crandc 20, 0, 2
; CHECK-NEXT: andis. 3, 3, 8
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: crand 21, 6, 2
-; CHECK-NEXT: xststdcdp 0, 1, 16
-; CHECK-NEXT: cror 21, 2, 21
+; CHECK-NEXT: crand 24, 6, 2
+; CHECK-NEXT: cror 21, 30, 24
; CHECK-NEXT: crnor 20, 21, 20
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
@@ -443,11 +443,11 @@ define i1 @isclass_1c0_float(float %x) nounwind {
; CHECK-LABEL: isclass_1c0_float:
; CHECK: # %bb.0:
; CHECK-NEXT: xststdcsp 0, 1, 127
+; CHECK-NEXT: xststdcsp 1, 1, 10
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: crnor 20, 0, 2
-; CHECK-NEXT: xststdcsp 0, 1, 10
-; CHECK-NEXT: crnor 20, 2, 20
-; CHECK-NEXT: isel 3, 0, 3, 20
+; CHECK-NEXT: crnor 24, 6, 20
+; CHECK-NEXT: isel 3, 0, 3, 24
; CHECK-NEXT: blr
%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 448)
ret i1 %1
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll b/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
index ac9641ff35b0cb5..52743884a18595c 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
@@ -114,21 +114,21 @@ define dso_local double @P10_Spill_CR_EQ(ptr %arg) local_unnamed_addr #0 {
; CHECK-NEXT: lwz r9, -4(r1)
; CHECK-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr7+eq
; CHECK-NEXT: crandc 4*cr7+eq, 4*cr7+un, 4*cr2+eq
-; CHECK-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr6+eq
+; CHECK-NEXT: crandc 4*cr6+eq, 4*cr5+lt, 4*cr6+eq
; CHECK-NEXT: setbc r7, 4*cr6+un
; CHECK-NEXT: setbc r8, 4*cr5+un
; CHECK-NEXT: lwz r12, 8(r1)
; CHECK-NEXT: xxlxor f2, f2, f2
; CHECK-NEXT: isel r3, r3, r5, 4*cr5+gt
; CHECK-NEXT: setbc r5, 4*cr7+gt
-; CHECK-NEXT: crnor 4*cr5+gt, 4*cr6+gt, 4*cr5+gt
-; CHECK-NEXT: crnor 4*cr6+gt, 4*cr7+lt, 4*cr7+eq
-; CHECK-NEXT: crnor 4*cr5+lt, 4*cr6+lt, 4*cr5+lt
+; CHECK-NEXT: crnor 4*cr1+lt, 4*cr6+gt, 4*cr5+gt
+; CHECK-NEXT: crnor lt, 4*cr7+lt, 4*cr7+eq
+; CHECK-NEXT: crnor 4*cr5+lt, 4*cr6+lt, 4*cr6+eq
; CHECK-NEXT: add r5, r7, r5
; CHECK-NEXT: add r5, r8, r5
-; CHECK-NEXT: isel r3, 0, r3, 4*cr5+gt
+; CHECK-NEXT: isel r3, 0, r3, 4*cr1+lt
; CHECK-NEXT: isel r4, 0, r4, 4*cr5+lt
-; CHECK-NEXT: isel r6, 0, r6, 4*cr6+gt
+; CHECK-NEXT: isellt r6, 0, r6
; CHECK-NEXT: mtocrf 128, r9
; CHECK-NEXT: mtfprd f0, r5
; CHECK-NEXT: isel r4, 0, r4, 4*cr5+eq
diff --git a/llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll b/llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll
index 801944315de009d..67a472e50929dc2 100644
--- a/llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll
@@ -25,9 +25,9 @@ define i1 @cmp(i8* %a, i8* %b) {
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: crandc 20, 0, 2
-; CHECK-NEXT: crand 21, 2, 4
-; CHECK-NEXT: cror 20, 21, 20
-; CHECK-NEXT: isel 3, 4, 3, 20
+; CHECK-NEXT: crand 24, 2, 4
+; CHECK-NEXT: cror 28, 24, 20
+; CHECK-NEXT: isel 3, 4, 3, 28
; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
index a2a5c6c5eafb7fc..2b68215cf586bd1 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
@@ -424,9 +424,9 @@ define i64 @setb17(i64 %a, i64 %b) {
; CHECK-PWR8-NEXT: cmpd r3, r4
; CHECK-PWR8-NEXT: li r5, -1
; CHECK-PWR8-NEXT: li r6, 1
+; CHECK-PWR8-NEXT: cmpld cr1, r3, r4
; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i64 %a, %b
%t2 = icmp sgt i64 %a, %b
@@ -448,9 +448,9 @@ define i64 @setb18(i64 %a, i64 %b) {
; CHECK-PWR8-NEXT: cmpd r3, r4
; CHECK-PWR8-NEXT: li r5, -1
; CHECK-PWR8-NEXT: li r6, 1
+; CHECK-PWR8-NEXT: cmpld cr1, r4, r3
; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i64 %b, %a
%t2 = icmp sgt i64 %a, %b
@@ -472,9 +472,9 @@ define i64 @setb19(i64 %a, i64 %b) {
; CHECK-PWR8-NEXT: cmpd r4, r3
; CHECK-PWR8-NEXT: li r5, -1
; CHECK-PWR8-NEXT: li r6, 1
+; CHECK-PWR8-NEXT: cmpld cr1, r3, r4
; CHECK-PWR8-NEXT: isellt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i64 %a, %b
%t2 = icmp slt i64 %b, %a
@@ -496,9 +496,9 @@ define i64 @setb20(i64 %a, i64 %b) {
; CHECK-PWR8-NEXT: cmpd r4, r3
; CHECK-PWR8-NEXT: li r5, -1
; CHECK-PWR8-NEXT: li r6, 1
+; CHECK-PWR8-NEXT: cmpld cr1, r4, r3
; CHECK-PWR8-NEXT: isellt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i64 %b, %a
%t2 = icmp slt i64 %b, %a
@@ -520,9 +520,9 @@ define i64 @setb21(i64 %a, i64 %b) {
; CHECK-PWR8-NEXT: cmpd r3, r4
; CHECK-PWR8-NEXT: li r5, 1
; CHECK-PWR8-NEXT: li r6, -1
+; CHECK-PWR8-NEXT: cmpld cr1, r3, r4
; CHECK-PWR8-NEXT: isellt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i64 %a, %b
%t2 = icmp slt i64 %a, %b
@@ -544,9 +544,9 @@ define i64 @setb22(i64 %a, i64 %b) {
; CHECK-PWR8-NEXT: cmpd r3, r4
; CHECK-PWR8-NEXT: li r5, 1
; CHECK-PWR8-NEXT: li r6, -1
+; CHECK-PWR8-NEXT: cmpld cr1, r4, r3
; CHECK-PWR8-NEXT: isellt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i64 %b, %a
%t2 = icmp slt i64 %a, %b
@@ -568,9 +568,9 @@ define i64 @setb23(i64 %a, i64 %b) {
; CHECK-PWR8-NEXT: cmpd r4, r3
; CHECK-PWR8-NEXT: li r5, 1
; CHECK-PWR8-NEXT: li r6, -1
+; CHECK-PWR8-NEXT: cmpld cr1, r3, r4
; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i64 %a, %b
%t2 = icmp sgt i64 %b, %a
@@ -592,9 +592,9 @@ define i64 @setb24(i64 %a, i64 %b) {
; CHECK-PWR8-NEXT: cmpd r4, r3
; CHECK-PWR8-NEXT: li r5, 1
; CHECK-PWR8-NEXT: li r6, -1
+; CHECK-PWR8-NEXT: cmpld cr1, r4, r3
; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmpld r4, r3
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i64 %b, %a
%t2 = icmp sgt i64 %b, %a
@@ -804,9 +804,9 @@ define i64 @setbsw3(i32 %a, i32 %b) {
; CHECK-PWR8-NEXT: cmpw r4, r3
; CHECK-PWR8-NEXT: li r5, 1
; CHECK-PWR8-NEXT: li r6, -1
+; CHECK-PWR8-NEXT: cmplw cr1, r3, r4
; CHECK-PWR8-NEXT: iselgt r5, r6, r5
-; CHECK-PWR8-NEXT: cmplw r3, r4
-; CHECK-PWR8-NEXT: iseleq r3, 0, r5
+; CHECK-PWR8-NEXT: isel r3, 0, r5, 4*cr1+eq
; CHECK-PWR8-NEXT: blr
%t1 = icmp eq i32 %a, %b
%t2 = icmp sgt i32 %b, %a
@@ -1150,9 +1150,9 @@ define i64 @setbf1(float %a, float %b) {
; CHECK-PWR8-NEXT: li r3, 0
; CHECK-PWR8-NEXT: li r4, 1
; CHECK-PWR8-NEXT: isellt r3, r4, r3
-; CHECK-PWR8-NEXT: fcmpu cr0, f1, f2
+; CHECK-PWR8-NEXT: fcmpu cr1, f1, f2
; CHECK-PWR8-NEXT: li r4, -1
-; CHECK-PWR8-NEXT: isellt r3, r4, r3
+; CHECK-PWR8-NEXT: isel r3, r4, r3, 4*cr1+lt
; CHECK-PWR8-NEXT: blr
%t1 = fcmp nnan olt float %a, %b
%t2 = fcmp nnan olt float %b, %a
@@ -1222,9 +1222,9 @@ define i64 @setbdf2(double %a, double %b) {
; CHECK-PWR8-NEXT: li r3, 0
; CHECK-PWR8-NEXT: li r4, -1
; CHECK-PWR8-NEXT: iselgt r3, r4, r3
-; CHECK-PWR8-NEXT: xscmpudp cr0, f2, f1
+; CHECK-PWR8-NEXT: xscmpudp cr1, f2, f1
; CHECK-PWR8-NEXT: li r4, 1
-; CHECK-PWR8-NEXT: isellt r3, r4, r3
+; CHECK-PWR8-NEXT: isel r3, r4, r3, 4*cr1+lt
; CHECK-PWR8-NEXT: blr
%t1 = fcmp nnan olt double %b, %a
%t2 = fcmp nnan ogt double %b, %a
@@ -1317,11 +1317,11 @@ define i64 @setbn2(double %a, double %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: fcmpu cr0, f1, f2
; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: xscmpudp cr1, f1, f2
; CHECK-NEXT: li r4, -1
; CHECK-NEXT: cror 4*cr5+lt, un, eq
-; CHECK-NEXT: xscmpudp cr0, f1, f2
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
-; CHECK-NEXT: isellt r3, r4, r3
+; CHECK-NEXT: isel r3, r4, r3, 4*cr1+lt
; CHECK-NEXT: blr
;
; CHECK-PWR8-LABEL: setbn2:
@@ -1330,9 +1330,9 @@ define i64 @setbn2(double %a, double %b) {
; CHECK-PWR8-NEXT: li r3, 1
; CHECK-PWR8-NEXT: li r4, -1
; CHECK-PWR8-NEXT: cror 4*cr5+lt, un, eq
-; CHECK-PWR8-NEXT: xscmpudp cr0, f1, f2
+; CHECK-PWR8-NEXT: xscmpudp cr1, f1, f2
; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt
-; CHECK-PWR8-NEXT: isellt r3, r4, r3
+; CHECK-PWR8-NEXT: isel r3, r4, r3, 4*cr1+lt
; CHECK-PWR8-NEXT: blr
%t1 = fcmp olt double %a, %b
%t2 = fcmp one double %a, %b
@@ -1378,11 +1378,11 @@ define void @setbn4(i128 %0, ptr %sel.out) {
; CHECK-NEXT: rldic r6, r6, 48, 15
; CHECK-NEXT: cmpld r4, r6
; CHECK-NEXT: crandc 4*cr5+lt, gt, eq
-; CHECK-NEXT: crandc 4*cr5+gt, eq, 4*cr1+eq
-; CHECK-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; CHECK-NEXT: crandc 4*cr6+lt, eq, 4*cr1+eq
+; CHECK-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
; CHECK-NEXT: rldicl. r4, r4, 16, 48
; CHECK-NEXT: li r4, -1
-; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
+; CHECK-NEXT: isel r3, 0, r3, 4*cr7+lt
; CHECK-NEXT: iseleq r3, r4, r3
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
@@ -1395,11 +1395,11 @@ define void @setbn4(i128 %0, ptr %sel.out) {
; CHECK-PWR8-NEXT: rldic r6, r6, 48, 15
; CHECK-PWR8-NEXT: cmpld r4, r6
; CHECK-PWR8-NEXT: crandc 4*cr5+lt, gt, eq
-; CHECK-PWR8-NEXT: crandc 4*cr5+gt, eq, 4*cr1+eq
+; CHECK-PWR8-NEXT: crandc 4*cr6+lt, eq, 4*cr1+eq
; CHECK-PWR8-NEXT: rldicl. r4, r4, 16, 48
; CHECK-PWR8-NEXT: li r4, -1
-; CHECK-PWR8-NEXT: crnor 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
-; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt
+; CHECK-PWR8-NEXT: crnor 4*cr7+lt, 4*cr6+lt, 4*cr5+lt
+; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr7+lt
; CHECK-PWR8-NEXT: iseleq r3, r4, r3
; CHECK-PWR8-NEXT: stw r3, 0(r5)
; CHECK-PWR8-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
index 7a6640fea2d1e42..989afa3563c98d6 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
@@ -2036,8 +2036,8 @@ define <2 x i64> @absd_int64_ugt(<2 x i64>, <2 x i64>) {
; CHECK-PWR7-NEXT: iselgt r7, r6, r5
; CHECK-PWR7-NEXT: std r7, -8(r1)
; CHECK-PWR7-NEXT: ld r7, -64(r1)
-; CHECK-PWR7-NEXT: cmpld r8, r7
-; CHECK-PWR7-NEXT: iselgt r5, r6, r5
+; CHECK-PWR7-NEXT: cmpld cr1, r8, r7
+; CHECK-PWR7-NEXT: isel r5, r6, r5, 4*cr1+gt
; CHECK-PWR7-NEXT: std r5, -16(r1)
; CHECK-PWR7-NEXT: sub r5, r4, r3
; CHECK-PWR7-NEXT: sub r3, r3, r4
diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
index 033728500abc8cf..b9a220a2f1ab234 100644
--- a/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
@@ -1297,10 +1297,10 @@ define i32 @test_fptoui_ppc_i32_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-NEXT: lis 3, -32768
; PC64LE-NEXT: fcmpo 0, 1, 0
; PC64LE-NEXT: crand 20, 2, 4
-; PC64LE-NEXT: crandc 21, 0, 2
-; PC64LE-NEXT: cror 20, 21, 20
-; PC64LE-NEXT: isel 30, 0, 3, 20
-; PC64LE-NEXT: bc 12, 20, .LBB31_2
+; PC64LE-NEXT: crandc 24, 0, 2
+; PC64LE-NEXT: cror 28, 24, 20
+; PC64LE-NEXT: isel 30, 0, 3, 28
+; PC64LE-NEXT: bc 12, 28, .LBB31_2
; PC64LE-NEXT: # %bb.1: # %entry
; PC64LE-NEXT: fmr 3, 0
; PC64LE-NEXT: .LBB31_2: # %entry
@@ -1334,10 +1334,10 @@ define i32 @test_fptoui_ppc_i32_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE9-NEXT: lis 3, -32768
; PC64LE9-NEXT: fcmpo 0, 1, 0
; PC64LE9-NEXT: crand 20, 2, 4
-; PC64LE9-NEXT: crandc 21, 0, 2
-; PC64LE9-NEXT: cror 20, 21, 20
-; PC64LE9-NEXT: isel 30, 0, 3, 20
-; PC64LE9-NEXT: bc 12, 20, .LBB31_2
+; PC64LE9-NEXT: crandc 24, 0, 2
+; PC64LE9-NEXT: cror 28, 24, 20
+; PC64LE9-NEXT: isel 30, 0, 3, 28
+; PC64LE9-NEXT: bc 12, 28, .LBB31_2
; PC64LE9-NEXT: # %bb.1: # %entry
; PC64LE9-NEXT: fmr 3, 0
; PC64LE9-NEXT: .LBB31_2: # %entry
@@ -1370,10 +1370,10 @@ define i32 @test_fptoui_ppc_i32_ppc_fp128(ppc_fp128 %first) #0 {
; PC64-NEXT: addis 3, 2, .LCPI31_1 at toc@ha
; PC64-NEXT: lfs 4, .LCPI31_1 at toc@l(3)
; PC64-NEXT: fcmpo 0, 1, 0
-; PC64-NEXT: crandc 21, 0, 2
+; PC64-NEXT: crandc 24, 0, 2
; PC64-NEXT: fcmpo 1, 2, 4
; PC64-NEXT: crand 20, 2, 4
-; PC64-NEXT: cror 8, 21, 20
+; PC64-NEXT: cror 8, 24, 20
; PC64-NEXT: fmr 3, 4
; PC64-NEXT: bc 12, 8, .LBB31_2
; PC64-NEXT: # %bb.1: # %entry
diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir b/llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
index 474c288bba88bf9..9431c61b957f554 100644
--- a/llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
+++ b/llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
@@ -23,8 +23,8 @@
; CHECK-NEXT: crnor 20, 7, 2
; CHECK-NEXT: fcmpu 0, 1, 0
; CHECK-NEXT: fcmpu 1, 1, 1
- ; CHECK-NEXT: crand 20, 2, 20
- ; CHECK-NEXT: bclr 12, 20, 0
+ ; CHECK-NEXT: crand 24, 2, 20
+ ; CHECK-NEXT: bclr 12, 24, 0
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: crnor 20, 7, 2
; CHECK-NEXT: bclr 12, 20, 0
diff --git a/llvm/test/CodeGen/PowerPC/pr48388.ll b/llvm/test/CodeGen/PowerPC/pr48388.ll
index 04efd989f5e86ca..086238694fac6c5 100644
--- a/llvm/test/CodeGen/PowerPC/pr48388.ll
+++ b/llvm/test/CodeGen/PowerPC/pr48388.ll
@@ -8,13 +8,13 @@ define i64 @julia_div_i64(i64 %0, i64 %1) local_unnamed_addr #0 {
; CHECK-NEXT: divd r5, r3, r4
; CHECK-NEXT: lis r6, -1592
; CHECK-NEXT: cmpdi r3, 0
+; CHECK-NEXT: cmpdi cr1, r4, 0
; CHECK-NEXT: ori r7, r6, 21321
; CHECK-NEXT: ori r6, r6, 65519
; CHECK-NEXT: rldic r7, r7, 4, 17
; CHECK-NEXT: rldic r6, r6, 4, 17
; CHECK-NEXT: iselgt r8, r6, r7
-; CHECK-NEXT: cmpdi r4, 0
-; CHECK-NEXT: iselgt r6, r6, r7
+; CHECK-NEXT: isel r6, r6, r7, 4*cr1+gt
; CHECK-NEXT: xor r6, r8, r6
; CHECK-NEXT: cntlzd r6, r6
; CHECK-NEXT: rldicl r6, r6, 58, 63
diff --git a/llvm/test/CodeGen/PowerPC/pr49509.ll b/llvm/test/CodeGen/PowerPC/pr49509.ll
index 7b6248c60ab4214..dec7059761aa803 100644
--- a/llvm/test/CodeGen/PowerPC/pr49509.ll
+++ b/llvm/test/CodeGen/PowerPC/pr49509.ll
@@ -40,9 +40,9 @@ define void @test() {
; CHECK-NEXT: .LBB0_6: # %bb66
; CHECK-NEXT: addi 3, 7, 0
; CHECK-NEXT: .LBB0_7: # %bb66
-; CHECK-NEXT: cror 20, 22, 2
+; CHECK-NEXT: cror 24, 22, 2
; CHECK-NEXT: stw 3, 0(3)
-; CHECK-NEXT: bc 12, 20, .LBB0_9
+; CHECK-NEXT: bc 12, 24, .LBB0_9
; CHECK-NEXT: # %bb.8: # %bb66
; CHECK-NEXT: ori 3, 6, 0
; CHECK-NEXT: b .LBB0_10
diff --git a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
index 912a74ba8df8fb5..e161bf61ff619ce 100644
--- a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
+++ b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
@@ -27,8 +27,8 @@ define void @test(ptr dereferenceable(4) %.ial, ptr noalias dereferenceable(4) %
; CHECK-P9-NEXT: slwi r4, r4, 4
; CHECK-P9-NEXT: addze r5, r5
; CHECK-P9-NEXT: sub r4, r4, r10
-; CHECK-P9-NEXT: cmpw r3, r4
-; CHECK-P9-NEXT: bgtlr cr0
+; CHECK-P9-NEXT: cmpw cr1, r3, r4
+; CHECK-P9-NEXT: bgtlr cr1
; CHECK-P9-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
; CHECK-P9-NEXT: extswsli r5, r5, 3
; CHECK-P9-NEXT: add r5, r8, r5
@@ -79,8 +79,8 @@ define void @test(ptr dereferenceable(4) %.ial, ptr noalias dereferenceable(4) %
; CHECK-P10-NEXT: slwi r4, r4, 4
; CHECK-P10-NEXT: addze r5, r5
; CHECK-P10-NEXT: sub r4, r4, r10
-; CHECK-P10-NEXT: cmpw r3, r4
-; CHECK-P10-NEXT: bgtlr cr0
+; CHECK-P10-NEXT: cmpw cr1, r3, r4
+; CHECK-P10-NEXT: bgtlr cr1
; CHECK-P10-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
; CHECK-P10-NEXT: extswsli r5, r5, 3
; CHECK-P10-NEXT: add r5, r8, r5
diff --git a/llvm/test/CodeGen/PowerPC/pzero-fp-xored.ll b/llvm/test/CodeGen/PowerPC/pzero-fp-xored.ll
index 7fac56fe04712d2..df972df13c65e95 100644
--- a/llvm/test/CodeGen/PowerPC/pzero-fp-xored.ll
+++ b/llvm/test/CodeGen/PowerPC/pzero-fp-xored.ll
@@ -66,8 +66,8 @@ define signext i32 @t3(ppc_fp128 %x) local_unnamed_addr #0 {
; CHECK-NEXT: fcmpu 0, 2, 0
; CHECK-NEXT: fcmpu 1, 1, 0
; CHECK-NEXT: crand 20, 6, 1
-; CHECK-NEXT: cror 20, 5, 20
-; CHECK-NEXT: isel 3, 4, 3, 20
+; CHECK-NEXT: cror 24, 5, 20
+; CHECK-NEXT: isel 3, 4, 3, 24
; CHECK-NEXT: blr
;
; CHECK-NVSXALT-LABEL: t3:
@@ -79,8 +79,8 @@ define signext i32 @t3(ppc_fp128 %x) local_unnamed_addr #0 {
; CHECK-NVSXALT-NEXT: fcmpu 0, 2, 0
; CHECK-NVSXALT-NEXT: fcmpu 1, 1, 0
; CHECK-NVSXALT-NEXT: crand 20, 6, 1
-; CHECK-NVSXALT-NEXT: cror 20, 5, 20
-; CHECK-NVSXALT-NEXT: isel 3, 4, 3, 20
+; CHECK-NVSXALT-NEXT: cror 24, 5, 20
+; CHECK-NVSXALT-NEXT: isel 3, 4, 3, 24
; CHECK-NVSXALT-NEXT: blr
entry:
%cmp = fcmp ogt ppc_fp128 %x, 0xM00000000000000000000000000000000
diff --git a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
index d5e77a5cda067f5..501182ca64a6dd7 100644
--- a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
+++ b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
@@ -1629,9 +1629,9 @@ define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, p
; CHECK-NEXT: fcmpu 0, 6, 8
; CHECK-NEXT: fcmpu 1, 5, 7
; CHECK-NEXT: crand 20, 6, 2
-; CHECK-NEXT: fcmpu 0, 2, 4
-; CHECK-NEXT: fcmpu 1, 1, 3
-; CHECK-NEXT: crand 21, 6, 2
+; CHECK-NEXT: fcmpu 6, 2, 4
+; CHECK-NEXT: fcmpu 7, 1, 3
+; CHECK-NEXT: crand 21, 30, 26
; CHECK-NEXT: crxor 20, 21, 20
; CHECK-NEXT: bc 12, 20, .LBB50_2
; CHECK-NEXT: # %bb.1: # %entry
@@ -1650,9 +1650,9 @@ define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, p
; CHECK-NO-ISEL-NEXT: fcmpu 0, 6, 8
; CHECK-NO-ISEL-NEXT: fcmpu 1, 5, 7
; CHECK-NO-ISEL-NEXT: crand 20, 6, 2
-; CHECK-NO-ISEL-NEXT: fcmpu 0, 2, 4
-; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 3
-; CHECK-NO-ISEL-NEXT: crand 21, 6, 2
+; CHECK-NO-ISEL-NEXT: fcmpu 6, 2, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 7, 1, 3
+; CHECK-NO-ISEL-NEXT: crand 21, 30, 26
; CHECK-NO-ISEL-NEXT: crxor 20, 21, 20
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB50_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
diff --git a/llvm/test/CodeGen/PowerPC/select.ll b/llvm/test/CodeGen/PowerPC/select.ll
index 49d55c7df524af6..c168e78203db463 100644
--- a/llvm/test/CodeGen/PowerPC/select.ll
+++ b/llvm/test/CodeGen/PowerPC/select.ll
@@ -189,11 +189,11 @@ define i64 @f4_sle_0(i64 %x) {
; CHECK-32: # %bb.0:
; CHECK-32-NEXT: cmplwi r3, 0
; CHECK-32-NEXT: cmpwi cr1, r3, 0
+; CHECK-32-NEXT: cmpwi cr6, r4, 0
; CHECK-32-NEXT: crandc 4*cr5+lt, 4*cr1+lt, eq
-; CHECK-32-NEXT: cmpwi cr1, r4, 0
; CHECK-32-NEXT: subfic r5, r4, 0
-; CHECK-32-NEXT: crand 4*cr5+gt, eq, 4*cr1+eq
-; CHECK-32-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; CHECK-32-NEXT: crand 4*cr7+lt, eq, 4*cr6+eq
+; CHECK-32-NEXT: cror 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
; CHECK-32-NEXT: subfze r6, r3
; CHECK-32-NEXT: bclr 12, 4*cr5+lt, 0
; CHECK-32-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
index 334379cda07ec1b..b967b72b138a792 100644
--- a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
@@ -15,8 +15,8 @@ define void @print_res() nounwind {
; CHECK-NEXT: li 3, 3
; CHECK-NEXT: isellt 3, 4, 3
; CHECK-NEXT: li 4, 1
-; CHECK-NEXT: cmpldi 3, 1
-; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: cmpldi 1, 3, 1
+; CHECK-NEXT: isel 3, 3, 4, 5
; CHECK-NEXT: li 4, 0
; CHECK-NEXT: mtctr 3
; CHECK-NEXT: stdu 1, -128(1)
diff --git a/llvm/test/CodeGen/PowerPC/smulfixsat.ll b/llvm/test/CodeGen/PowerPC/smulfixsat.ll
index 9e371d499da35a1..1038c7b5b43a5dd 100644
--- a/llvm/test/CodeGen/PowerPC/smulfixsat.ll
+++ b/llvm/test/CodeGen/PowerPC/smulfixsat.ll
@@ -26,6 +26,7 @@ define i32 @func2(i32 %x, i32 %y) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: mulhw. 6, 3, 4
; CHECK-NEXT: lis 5, 32767
+; CHECK-NEXT: cmpwi 1, 6, -1
; CHECK-NEXT: mullw 3, 3, 4
; CHECK-NEXT: rotlwi 3, 3, 31
; CHECK-NEXT: ori 4, 5, 65535
@@ -35,9 +36,8 @@ define i32 @func2(i32 %x, i32 %y) nounwind {
; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: addi 3, 4, 0
; CHECK-NEXT: .LBB1_2:
-; CHECK-NEXT: cmpwi 6, -1
; CHECK-NEXT: lis 4, -32768
-; CHECK-NEXT: bc 12, 0, .LBB1_3
+; CHECK-NEXT: bc 12, 4, .LBB1_3
; CHECK-NEXT: blr
; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: addi 3, 4, 0
diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll
index 4bfc413a5a2aa23..fbd9510e37cf406 100644
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -392,10 +392,10 @@ define i1 @test_fcmpult(float %a, float %b) #0 {
; CHECK-NEXT: efscmpeq 0, 3, 3
; CHECK-NEXT: efscmpeq 1, 4, 4
; CHECK-NEXT: crnand 20, 5, 1
-; CHECK-NEXT: efscmplt 0, 3, 4
+; CHECK-NEXT: efscmplt 6, 3, 4
; CHECK-NEXT: li 5, 1
-; CHECK-NEXT: crnor 20, 1, 20
-; CHECK-NEXT: bc 12, 20, .LBB18_2
+; CHECK-NEXT: crnor 28, 25, 20
+; CHECK-NEXT: bc 12, 28, .LBB18_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: ori 3, 5, 0
; CHECK-NEXT: blr
@@ -1410,9 +1410,9 @@ define i1 @test_dcmpge(double %a, double %b) #0 {
; SPE-NEXT: efdcmpeq 0, 4, 4
; SPE-NEXT: efdcmpeq 1, 3, 3
; SPE-NEXT: efdcmplt 5, 3, 4
-; SPE-NEXT: crand 20, 5, 1
-; SPE-NEXT: crorc 20, 21, 20
-; SPE-NEXT: bc 12, 20, .LBB47_2
+; SPE-NEXT: crand 24, 5, 1
+; SPE-NEXT: crorc 28, 21, 24
+; SPE-NEXT: bc 12, 28, .LBB47_2
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll b/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
index c8278e58ad064cb..a50675306059065 100644
--- a/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
@@ -30,9 +30,9 @@ define dso_local signext i32 @main(i32 signext %argc, ptr nocapture readnone %ar
; CHECK-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: crmove 20, 10
-; CHECK-NEXT: crorc 20, 10, 2
-; CHECK-NEXT: crmove 21, 2
-; CHECK-NEXT: bc 4, 20, .LBB0_4
+; CHECK-NEXT: crorc 28, 10, 2
+; CHECK-NEXT: crmove 24, 2
+; CHECK-NEXT: bc 4, 28, .LBB0_4
; CHECK-NEXT: # %bb.2: # %if.end5
; CHECK-NEXT: addis 3, 2, .L.str at toc@ha
; CHECK-NEXT: addi 3, 3, .L.str at toc@l
@@ -76,12 +76,12 @@ define dso_local signext i32 @main(i32 signext %argc, ptr nocapture readnone %ar
; BE-NEXT: addi 3, 31, 128
; BE-NEXT: bl _setjmp
; BE-NEXT: nop
-; BE-NEXT: crmove 20, 10
; BE-NEXT: # kill: def $r3 killed $r3 killed $x3
; BE-NEXT: cmpwi 3, 0
-; BE-NEXT: crorc 20, 10, 2
-; BE-NEXT: crmove 21, 2
-; BE-NEXT: bc 4, 20, .LBB0_4
+; BE-NEXT: crorc 28, 10, 2
+; BE-NEXT: crmove 20, 10
+; BE-NEXT: crmove 24, 2
+; BE-NEXT: bc 4, 28, .LBB0_4
; BE-NEXT: # %bb.2: # %if.end5
; BE-NEXT: addis 3, 2, .L.str at toc@ha
; BE-NEXT: addi 3, 3, .L.str at toc@l
diff --git a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
index 48098e3a277c184..b4e7ca4f943ce2d 100644
--- a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
@@ -54,15 +54,15 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32-NEXT: crnor 21, 30, 10
; PPC32-NEXT: mulhwu. 26, 9, 4
; PPC32-NEXT: stw 25, 36(1) # 4-byte Folded Spill
-; PPC32-NEXT: crorc 20, 20, 6
-; PPC32-NEXT: stw 27, 44(1) # 4-byte Folded Spill
; PPC32-NEXT: crorc 21, 21, 26
+; PPC32-NEXT: stw 27, 44(1) # 4-byte Folded Spill
+; PPC32-NEXT: crorc 21, 21, 2
; PPC32-NEXT: stw 28, 48(1) # 4-byte Folded Spill
; PPC32-NEXT: mulhwu 30, 6, 10
; PPC32-NEXT: stw 12, 20(1)
-; PPC32-NEXT: crorc 20, 20, 22
-; PPC32-NEXT: crorc 21, 21, 2
; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: crorc 20, 20, 6
+; PPC32-NEXT: crorc 20, 20, 22
; PPC32-NEXT: mullw 26, 5, 10
; PPC32-NEXT: addc 30, 26, 30
; PPC32-NEXT: mulhwu 29, 5, 10
@@ -71,30 +71,30 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; PPC32-NEXT: mullw 22, 7, 6
; PPC32-NEXT: mulhwu 0, 6, 9
; PPC32-NEXT: mulhwu 12, 5, 9
-; PPC32-NEXT: mulhwu 27, 8, 6
; PPC32-NEXT: mullw 25, 6, 9
; PPC32-NEXT: mullw 24, 5, 9
; PPC32-NEXT: mullw 5, 9, 4
; PPC32-NEXT: add 9, 22, 23
-; PPC32-NEXT: add 9, 27, 9
-; PPC32-NEXT: cmplw 1, 9, 27
-; PPC32-NEXT: cror 20, 20, 4
; PPC32-NEXT: mullw 23, 3, 10
; PPC32-NEXT: add 26, 23, 5
; PPC32-NEXT: addc 5, 25, 30
; PPC32-NEXT: addze 0, 0
; PPC32-NEXT: or. 3, 4, 3
; PPC32-NEXT: mulhwu 28, 4, 10
-; PPC32-NEXT: mcrf 1, 0
+; PPC32-NEXT: mcrf 7, 0
; PPC32-NEXT: addc 3, 29, 0
; PPC32-NEXT: add 26, 28, 26
-; PPC32-NEXT: cmplw 6, 26, 28
-; PPC32-NEXT: cror 21, 21, 24
; PPC32-NEXT: mullw 30, 4, 10
; PPC32-NEXT: or. 4, 8, 7
; PPC32-NEXT: addze 4, 11
; PPC32-NEXT: addc 7, 24, 3
-; PPC32-NEXT: crnor 22, 2, 6
+; PPC32-NEXT: crnor 22, 2, 30
+; PPC32-NEXT: mulhwu 27, 8, 6
+; PPC32-NEXT: add 9, 27, 9
+; PPC32-NEXT: cmplw 1, 9, 27
+; PPC32-NEXT: cror 20, 20, 4
+; PPC32-NEXT: cmplw 1, 26, 28
+; PPC32-NEXT: cror 21, 21, 4
; PPC32-NEXT: mullw 27, 8, 6
; PPC32-NEXT: adde 8, 12, 4
; PPC32-NEXT: addc 3, 30, 27
diff --git a/llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
index f708da86444b2ba..444c2723fd4657d 100644
--- a/llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
@@ -245,10 +245,10 @@ define i1 @test_urem_oversized(i66 %X) nounwind {
; PPC-NEXT: cmplwi 1, 10, 13
; PPC-NEXT: rlwinm 3, 3, 31, 31, 31
; PPC-NEXT: crand 20, 6, 0
-; PPC-NEXT: crandc 21, 4, 6
+; PPC-NEXT: crandc 24, 4, 6
; PPC-NEXT: rlwimi. 3, 6, 1, 30, 30
-; PPC-NEXT: cror 20, 20, 21
-; PPC-NEXT: crnand 20, 2, 20
+; PPC-NEXT: cror 28, 20, 24
+; PPC-NEXT: crnand 20, 2, 28
; PPC-NEXT: li 3, 1
; PPC-NEXT: bc 12, 20, .LBB5_1
; PPC-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/vec-min-max.ll b/llvm/test/CodeGen/PowerPC/vec-min-max.ll
index db83fd187bed33e..de1790c5d103ea4 100644
--- a/llvm/test/CodeGen/PowerPC/vec-min-max.ll
+++ b/llvm/test/CodeGen/PowerPC/vec-min-max.ll
@@ -74,8 +74,8 @@ define <2 x i64> @getsmaxi64(<2 x i64> %a, <2 x i64> %b) {
; NOP8VEC-NEXT: iselgt 5, 4, 3
; NOP8VEC-NEXT: std 5, -8(1)
; NOP8VEC-NEXT: ld 5, -32(1)
-; NOP8VEC-NEXT: cmpd 6, 5
-; NOP8VEC-NEXT: iselgt 3, 4, 3
+; NOP8VEC-NEXT: cmpd 1, 6, 5
+; NOP8VEC-NEXT: isel 3, 4, 3, 5
; NOP8VEC-NEXT: std 3, -16(1)
; NOP8VEC-NEXT: addi 3, 1, -16
; NOP8VEC-NEXT: lxvd2x 0, 0, 3
@@ -191,8 +191,8 @@ define <2 x i64> @getsmini64(<2 x i64> %a, <2 x i64> %b) {
; NOP8VEC-NEXT: isellt 5, 4, 3
; NOP8VEC-NEXT: std 5, -8(1)
; NOP8VEC-NEXT: ld 5, -32(1)
-; NOP8VEC-NEXT: cmpd 6, 5
-; NOP8VEC-NEXT: isellt 3, 4, 3
+; NOP8VEC-NEXT: cmpd 1, 6, 5
+; NOP8VEC-NEXT: isel 3, 4, 3, 4
; NOP8VEC-NEXT: std 3, -16(1)
; NOP8VEC-NEXT: addi 3, 1, -16
; NOP8VEC-NEXT: lxvd2x 0, 0, 3
@@ -267,9 +267,9 @@ define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
; NOP8VEC-NEXT: cmpld 4, 8
; NOP8VEC-NEXT: cmpd 1, 4, 8
; NOP8VEC-NEXT: crandc 20, 4, 2
-; NOP8VEC-NEXT: cmpld 1, 3, 7
-; NOP8VEC-NEXT: crand 21, 2, 4
-; NOP8VEC-NEXT: cror 20, 21, 20
+; NOP8VEC-NEXT: cmpld 6, 3, 7
+; NOP8VEC-NEXT: crand 28, 2, 24
+; NOP8VEC-NEXT: cror 20, 28, 20
; NOP8VEC-NEXT: isel 3, 3, 7, 20
; NOP8VEC-NEXT: isel 4, 4, 8, 20
; NOP8VEC-NEXT: std 3, -32(1)
diff --git a/llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll b/llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
index e9bb6116e68c268..011c4d5ff9fd2f3 100644
--- a/llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
@@ -51,8 +51,8 @@ define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
; CHECK-NEXT: iselgt 5, 4, 3
; CHECK-NEXT: std 5, -8(1)
; CHECK-NEXT: ld 5, -32(1)
-; CHECK-NEXT: cmpd 6, 5
-; CHECK-NEXT: iselgt 3, 4, 3
+; CHECK-NEXT: cmpd 1, 6, 5
+; CHECK-NEXT: isel 3, 4, 3, 5
; CHECK-NEXT: std 3, -16(1)
; CHECK-NEXT: addi 3, 1, -16
; CHECK-NEXT: lxvd2x 0, 0, 3
@@ -74,8 +74,8 @@ define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
; CHECK-BE-NEXT: iselgt 5, 4, 3
; CHECK-BE-NEXT: std 5, -8(1)
; CHECK-BE-NEXT: ld 5, -32(1)
-; CHECK-BE-NEXT: cmpd 6, 5
-; CHECK-BE-NEXT: iselgt 3, 4, 3
+; CHECK-BE-NEXT: cmpd 1, 6, 5
+; CHECK-BE-NEXT: isel 3, 4, 3, 5
; CHECK-BE-NEXT: std 3, -16(1)
; CHECK-BE-NEXT: addi 3, 1, -16
; CHECK-BE-NEXT: lxvd2x 34, 0, 3
@@ -104,8 +104,8 @@ define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
; CHECK-NEXT: iselgt 5, 4, 3
; CHECK-NEXT: std 5, -8(1)
; CHECK-NEXT: ld 5, -32(1)
-; CHECK-NEXT: cmpld 6, 5
-; CHECK-NEXT: iselgt 3, 4, 3
+; CHECK-NEXT: cmpld 1, 6, 5
+; CHECK-NEXT: isel 3, 4, 3, 5
; CHECK-NEXT: std 3, -16(1)
; CHECK-NEXT: addi 3, 1, -16
; CHECK-NEXT: lxvd2x 0, 0, 3
@@ -127,8 +127,8 @@ define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
; CHECK-BE-NEXT: iselgt 5, 4, 3
; CHECK-BE-NEXT: std 5, -8(1)
; CHECK-BE-NEXT: ld 5, -32(1)
-; CHECK-BE-NEXT: cmpld 6, 5
-; CHECK-BE-NEXT: iselgt 3, 4, 3
+; CHECK-BE-NEXT: cmpld 1, 6, 5
+; CHECK-BE-NEXT: isel 3, 4, 3, 5
; CHECK-BE-NEXT: std 3, -16(1)
; CHECK-BE-NEXT: addi 3, 1, -16
; CHECK-BE-NEXT: lxvd2x 34, 0, 3
diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
index ff7f1fc9029813d..0c96335c0cb609e 100644
--- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
@@ -12178,18 +12178,18 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 2
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 2
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 2
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -12312,18 +12312,18 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 3
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 3
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 3
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -12446,18 +12446,18 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 3
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 3
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 3
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -12580,18 +12580,18 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 4
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 4
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 4
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -12714,18 +12714,18 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 4
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 4
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 4
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -12848,18 +12848,18 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 5
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 5
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 5
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -12982,18 +12982,18 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 5
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 5
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 5
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -13116,18 +13116,18 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 6
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 6
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 6
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -13250,18 +13250,18 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 6
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 6
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 6
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -13384,18 +13384,18 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 7
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 7
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 7
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -13518,18 +13518,18 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 7
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 7
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 7
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -13652,18 +13652,18 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 8
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 8
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 8
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -13786,18 +13786,18 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 8
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 8
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 8
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -13920,18 +13920,18 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 9
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 9
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 9
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -14054,18 +14054,18 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 9
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 9
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 9
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -14188,18 +14188,18 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 10
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 10
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 10
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -14322,18 +14322,18 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 10
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 10
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 10
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -14456,18 +14456,18 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 11
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 11
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 11
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -14590,18 +14590,18 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 11
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 11
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 11
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -14724,18 +14724,18 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 12
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 12
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 12
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -14858,18 +14858,18 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 12
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 12
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 12
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -14992,18 +14992,18 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 13
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 13
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 13
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -15126,18 +15126,18 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 13
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 13
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 13
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -15260,18 +15260,18 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 14
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 14
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 14
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -15394,18 +15394,18 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 14
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 14
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 14
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -15528,18 +15528,18 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 15
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 15
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 15
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -15662,18 +15662,18 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 15
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 15
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 15
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -15796,18 +15796,18 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 16
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 16
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 16
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -15930,18 +15930,18 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 16
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 16
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 16
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -16064,18 +16064,18 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 17
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 17
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 17
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -16198,18 +16198,18 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 17
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 17
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 17
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -16332,18 +16332,18 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 18
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 18
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 18
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -16466,18 +16466,18 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 18
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 18
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 18
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -16600,18 +16600,18 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 19
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 19
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 19
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -16734,18 +16734,18 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 19
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 19
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 19
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -16868,18 +16868,18 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 20
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 20
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 20
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -17002,18 +17002,18 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 20
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 20
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 20
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -17136,18 +17136,18 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 21
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 21
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 21
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -17270,18 +17270,18 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 21
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 21
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 21
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -17404,18 +17404,18 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 22
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 22
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 22
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -17538,18 +17538,18 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 22
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 22
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 22
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -17672,18 +17672,18 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 23
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 23
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 23
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -17806,18 +17806,18 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 23
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 23
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 23
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -17940,18 +17940,18 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 24
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 24
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 24
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -18074,18 +18074,18 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 24
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 24
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 24
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -18208,18 +18208,18 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 25
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 25
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 25
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -18342,18 +18342,18 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 25
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 25
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 25
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -18476,18 +18476,18 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 26
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 26
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 26
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -18610,18 +18610,18 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 26
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 26
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 26
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -18744,18 +18744,18 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 27
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 27
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 27
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -18878,18 +18878,18 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 27
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 27
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 27
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -19012,18 +19012,18 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 28
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 28
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 28
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -19146,18 +19146,18 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 28
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 28
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 28
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -19280,18 +19280,18 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 29
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 29
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 29
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -19414,18 +19414,18 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 29
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 29
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 29
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -19548,18 +19548,18 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 30
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 30
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 30
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -19682,18 +19682,18 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 30
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 30
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 30
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -19816,18 +19816,18 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 31
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 31
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 31
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -19950,18 +19950,18 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 31
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 31
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 31
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -20084,18 +20084,18 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 32
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 32
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 32
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -20218,18 +20218,18 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 32
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 32
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 32
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -20352,18 +20352,18 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 33
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 33
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 33
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -20486,18 +20486,18 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 33
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 33
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 33
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -20620,18 +20620,18 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 34
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 34
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 34
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -20754,18 +20754,18 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 34
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 34
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 34
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -20888,18 +20888,18 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 35
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 35
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 35
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -21022,18 +21022,18 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 35
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 35
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 35
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -21156,18 +21156,18 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 36
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 36
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 36
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -21290,18 +21290,18 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 36
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 36
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 36
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -21424,18 +21424,18 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 37
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 37
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 37
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -21558,18 +21558,18 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 37
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 37
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 37
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -21692,18 +21692,18 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 38
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 38
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 38
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -21826,18 +21826,18 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 38
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 38
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 38
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -21960,18 +21960,18 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 39
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 39
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 39
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -22094,18 +22094,18 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 39
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 39
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 39
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -22228,18 +22228,18 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 40
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 40
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 40
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -22362,18 +22362,18 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 40
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 40
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 40
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -22496,18 +22496,18 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 41
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 41
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 41
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -22630,18 +22630,18 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 41
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 41
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 41
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -22764,18 +22764,18 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 42
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 42
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 42
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -22898,18 +22898,18 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 42
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 42
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 42
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -23032,18 +23032,18 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 43
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 43
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 43
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -23166,18 +23166,18 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 43
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 43
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 43
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -23300,18 +23300,18 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 44
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 44
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 44
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -23434,18 +23434,18 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 44
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 44
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 44
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -23568,18 +23568,18 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 45
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 45
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 45
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -23702,18 +23702,18 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 45
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 45
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 45
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -23836,18 +23836,18 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 46
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 46
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 46
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -23970,18 +23970,18 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 46
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 46
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 46
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -24104,18 +24104,18 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 47
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 47
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 47
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -24238,18 +24238,18 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 47
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 47
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 47
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -24372,18 +24372,18 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 48
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 48
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 48
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -24506,18 +24506,18 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 48
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 48
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 48
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -24640,18 +24640,18 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 49
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 49
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 49
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -24774,18 +24774,18 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 49
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 49
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 49
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -24908,18 +24908,18 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 50
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 50
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 50
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -25042,18 +25042,18 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 50
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 50
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 50
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -25176,18 +25176,18 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 51
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 51
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 51
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -25310,18 +25310,18 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 51
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 51
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 51
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -25444,18 +25444,18 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 52
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 52
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 52
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -25578,18 +25578,18 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 52
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 52
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 52
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -25712,18 +25712,18 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 53
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 53
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 53
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -25846,18 +25846,18 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 53
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 53
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 53
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -25980,18 +25980,18 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 54
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 54
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 54
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -26114,18 +26114,18 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 54
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 54
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 54
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -26248,18 +26248,18 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 55
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 55
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 55
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -26382,18 +26382,18 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 55
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 55
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 55
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -26516,18 +26516,18 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 56
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 56
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 56
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -26650,18 +26650,18 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 56
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 56
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 56
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -26784,18 +26784,18 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 57
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 57
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 57
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -26918,18 +26918,18 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 57
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 57
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 57
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -27052,18 +27052,18 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 58
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 58
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 58
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -27186,18 +27186,18 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 58
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 58
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 58
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -27320,18 +27320,18 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 59
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 59
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 59
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -27454,18 +27454,18 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 59
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 59
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 59
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -27588,18 +27588,18 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 60
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 60
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 60
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -27722,18 +27722,18 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 60
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 60
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 60
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -27856,18 +27856,18 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 61
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 61
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 61
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -27990,18 +27990,18 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 61
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 61
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 61
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -28124,18 +28124,18 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 62
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 62
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 62
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -28258,18 +28258,18 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 62
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 62
+; PWR7-NEXT: isel 3, 5, 4, 5
; PWR7-NEXT: iselgt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 62
-; PWR7-NEXT: iselgt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
@@ -28392,18 +28392,18 @@ define <2 x i64> @ult_63_v2i64(<2 x i64> %0) {
; PWR7-NEXT: addi 3, 1, -32
; PWR7-NEXT: li 5, -1
; PWR7-NEXT: stxvd2x 34, 0, 3
-; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: ld 3, -32(1)
-; PWR7-NEXT: popcntd 4, 4
+; PWR7-NEXT: ld 4, -24(1)
; PWR7-NEXT: popcntd 3, 3
+; PWR7-NEXT: popcntd 4, 4
; PWR7-NEXT: cmpldi 4, 63
; PWR7-NEXT: li 4, 0
+; PWR7-NEXT: cmpldi 1, 3, 63
+; PWR7-NEXT: isel 3, 5, 4, 4
; PWR7-NEXT: isellt 6, 5, 4
-; PWR7-NEXT: cmpldi 3, 63
-; PWR7-NEXT: isellt 3, 5, 4
-; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: std 3, -16(1)
; PWR7-NEXT: addi 3, 1, -16
+; PWR7-NEXT: std 6, -8(1)
; PWR7-NEXT: lxvd2x 34, 0, 3
; PWR7-NEXT: blr
;
diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll
index 32cbfd6d810acca..52851f2d78ae3ca 100644
--- a/llvm/test/CodeGen/PowerPC/vsx.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx.ll
@@ -2136,8 +2136,8 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: isellt r5, r4, r3
; CHECK-NEXT: std r5, -8(r1)
; CHECK-NEXT: ld r5, -32(r1)
-; CHECK-NEXT: cmpld r6, r5
-; CHECK-NEXT: isellt r3, r4, r3
+; CHECK-NEXT: cmpld cr1, r6, r5
+; CHECK-NEXT: isel r3, r4, r3, 4*cr1+lt
; CHECK-NEXT: std r3, -16(r1)
; CHECK-NEXT: addi r3, r1, -16
; CHECK-NEXT: lxvd2x v2, 0, r3
@@ -2158,8 +2158,8 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
; CHECK-REG-NEXT: isellt r5, r4, r3
; CHECK-REG-NEXT: std r5, -8(r1)
; CHECK-REG-NEXT: ld r5, -32(r1)
-; CHECK-REG-NEXT: cmpld r6, r5
-; CHECK-REG-NEXT: isellt r3, r4, r3
+; CHECK-REG-NEXT: cmpld cr1, r6, r5
+; CHECK-REG-NEXT: isel r3, r4, r3, 4*cr1+lt
; CHECK-REG-NEXT: std r3, -16(r1)
; CHECK-REG-NEXT: addi r3, r1, -16
; CHECK-REG-NEXT: lxvd2x v2, 0, r3
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