[llvm] ae3ba72 - [RISCV][GlobalISel] Select G_FRAME_INDEX (#68254)
via llvm-commits
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Tue Oct 17 17:56:46 PDT 2023
Author: Nitin John Raj
Date: 2023-10-17T17:56:42-07:00
New Revision: ae3ba725b7902ec9058a07de0db49f17419c6daa
URL: https://github.com/llvm/llvm-project/commit/ae3ba725b7902ec9058a07de0db49f17419c6daa
DIFF: https://github.com/llvm/llvm-project/commit/ae3ba725b7902ec9058a07de0db49f17419c6daa.diff
LOG: [RISCV][GlobalISel] Select G_FRAME_INDEX (#68254)
This patch is a bandage to get G_FRAME_INDEX working. We could import
the SelectionDAG patterns for the ComplexPattern FrameAddrRegImm, and
perhaps we will do that in the future. For now we just select it as an
addition with 0.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 12d1d64212720ff..2d698736080d9fa 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -194,6 +194,14 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
case TargetOpcode::G_SEXT_INREG:
return selectSExtInreg(MI, MIB);
+ case TargetOpcode::G_FRAME_INDEX: {
+ // TODO: We may want to replace this code with the SelectionDAG patterns,
+ // which fail to get imported because it uses FrameAddrRegImm, which is a
+ // ComplexPattern
+ MI.setDesc(TII.get(RISCV::ADDI));
+ MI.addOperand(MachineOperand::CreateImm(0));
+ return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+ }
case TargetOpcode::G_SELECT:
return selectSelect(MI, MIB, MRI);
default:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index e2cf461a1eb8e22..c8073199ade1bd3 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -135,6 +135,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_STORE:
break;
case TargetOpcode::G_CONSTANT:
+ case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE:
case TargetOpcode::G_BRCOND:
OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
new file mode 100644
index 000000000000000..20747bd1876180c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+ %x = alloca i32, align 4
+ ret ptr %x
+ }
+
+...
+---
+name: frame_index
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: frame_index
+ ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+ ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+ $x10 = COPY %0(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
new file mode 100644
index 000000000000000..dc265bda0a68894
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+ %x = alloca i32, align 4
+ ret ptr %x
+ }
+
+...
+---
+name: frame_index
+legalized: true
+regBankSelected: true
+registers:
+ - { id: 0, class: gprb, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: frame_index
+ ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+ ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+ $x10 = COPY %0(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
new file mode 100644
index 000000000000000..f701ef616962552
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect %s -o - \
+# RUN: | FileCheck %s
+--- |
+ define ptr @frame_index() {
+ entry:
+ %x = alloca i32, align 4
+ ret ptr %x
+ }
+
+...
+---
+name: frame_index
+legalized: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+stack:
+ - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body: |
+ bb.1.entry:
+ ; CHECK-LABEL: name: frame_index
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %stack.0.x
+ ; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = G_FRAME_INDEX %stack.0.x
+ $x10 = COPY %0(p0)
+ PseudoRET implicit $x10
+
+...
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