[llvm] 2a40ec2 - [DAG] SimplifyDemandedBits - fix isOperationLegal typo in D146121

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-10-17T17:50:12+01:00
New Revision: 2a40ec2d3e4d2af0222156022256cdee1ae6bb56

URL: https://github.com/llvm/llvm-project/commit/2a40ec2d3e4d2af0222156022256cdee1ae6bb56
DIFF: https://github.com/llvm/llvm-project/commit/2a40ec2d3e4d2af0222156022256cdee1ae6bb56.diff

LOG: [DAG] SimplifyDemandedBits - fix isOperationLegal typo in D146121

We need to check that the simplified ISD::SRL node is legal, not the old one

Noticed while trying to isolate the regressions in D155472

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index c0e88051dc427f1..8b4f3159499122a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1897,7 +1897,7 @@ bool TargetLowering::SimplifyDemandedBits(
         if (isNarrowingProfitable(VT, HalfVT) &&
             isTypeDesirableForOp(ISD::SRL, HalfVT) &&
             isTruncateFree(VT, HalfVT) && isZExtFree(HalfVT, VT) &&
-            (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) &&
+            (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) &&
             ((InDemandedMask.countLeadingZeros() >= (BitWidth / 2)) ||
              TLO.DAG.MaskedValueIsZero(Op0, HiBits))) {
           SDValue NewOp = TLO.DAG.getNode(ISD::TRUNCATE, dl, HalfVT, Op0);