[llvm] [AMDGPU] support 64-bit immediates in SIInstrInfo::FoldImmediate (PR #69260)

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git-clang-format --diff fa7d6a0fa5eafabde83f07065eb46eb144b715de fcd9aa9b8279e5bc21b5b5173f82c3546be154dc -- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c0af9a9ad..2ec9eb3af 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3222,20 +3222,20 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
   auto getImmFor = [ImmOp](const MachineOperand &UseOp) -> int64_t {
     int64_t Imm = ImmOp->getImm();
     switch (UseOp.getSubReg()) {
-      default:
-        return Imm;
-      case AMDGPU::sub0:
-        return Lo_32(Imm);
-      case AMDGPU::sub1:
-        return Hi_32(Imm);
-      case AMDGPU::lo16:
-        return APInt(16, Imm).getSExtValue();
-      case AMDGPU::hi16:
-        return APInt(32, Imm).ashr(16).getSExtValue();
-      case AMDGPU::sub1_lo16:
-        return APInt(16, Hi_32(Imm)).getSExtValue();
-      case AMDGPU::sub1_hi16:
-        return APInt(32, Hi_32(Imm)).ashr(16).getSExtValue();
+    default:
+      return Imm;
+    case AMDGPU::sub0:
+      return Lo_32(Imm);
+    case AMDGPU::sub1:
+      return Hi_32(Imm);
+    case AMDGPU::lo16:
+      return APInt(16, Imm).getSExtValue();
+    case AMDGPU::hi16:
+      return APInt(32, Imm).ashr(16).getSExtValue();
+    case AMDGPU::sub1_lo16:
+      return APInt(16, Hi_32(Imm)).getSExtValue();
+    case AMDGPU::sub1_hi16:
+      return APInt(32, Hi_32(Imm)).ashr(16).getSExtValue();
     }
   };
 
@@ -3250,10 +3250,10 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
     bool Is16Bit = OpSize == 2;
     bool Is64Bit = OpSize == 8;
     bool isVGPRCopy = RI.isVGPR(*MRI, DstReg);
-    unsigned NewOpc = isVGPRCopy ? Is64Bit ? AMDGPU::V_MOV_B64_PSEUDO
-                                           : AMDGPU::V_MOV_B32_e32
-                                 : Is64Bit ? AMDGPU::S_MOV_B64_IMM_PSEUDO
-                                           : AMDGPU::S_MOV_B32;
+    unsigned NewOpc =
+        isVGPRCopy ? Is64Bit ? AMDGPU::V_MOV_B64_PSEUDO : AMDGPU::V_MOV_B32_e32
+        : Is64Bit  ? AMDGPU::S_MOV_B64_IMM_PSEUDO
+                   : AMDGPU::S_MOV_B32;
     APInt Imm(Is64Bit ? 64 : 32, getImmFor(UseMI.getOperand(1)));
 
     if (RI.isAGPR(*MRI, DstReg)) {

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https://github.com/llvm/llvm-project/pull/69260