[llvm] [RISCV] Combine trunc (srl zext (x), zext (y)) to srl (x, umin (y, scalarsizeinbits(y) - 1)) (PR #69092)

[via llvm-commits]

LWenH wrote:

> Specifically I think #65728 is fine because sra has the property that ` ∀ n : nat. (sra x, sew-1) = (sra x, sew-1+n)`, but srl doesn't i.e. `(srl x, sew-1) != (srl x, sew)`

Yeah, still big difference between vsrl and vsra, but through this I think lg2(sew) is still not enough for vsrl, logical right shift can reach the sew bits, that’s interesting.

https://github.com/llvm/llvm-project/pull/69092