[llvm] [RISCV] Combine trunc (srl zext (x), zext (y)) to srl (x, umin (y, scalarsizeinbits(y) - 1)) (PR #69092)

[via llvm-commits]

LWenH wrote:

> It this valid for y > 7? E.g. `(trunc (srl (zext 128 to i32), (zext 8 to i32)) to i8) = 0`, but if we clip y to `umin(y, scalarsizeinbits(y) - 1)` then we get `(srl 128, 7) = 1`
> 
> https://alive2.llvm.org/ce/z/T28oxz

Yeah, I think you are right. Even though the rvv only utilize the **lg2(sew)** bits as the shift amount. But the result are still different after zext, this this only work for arithmetic right shift, the transformation for y > 7 is still inconsistent. Thank you for verifying this case. 

- Close this pull request.

https://github.com/llvm/llvm-project/pull/69092