[llvm] [DAG] Expand vXi1 add/sub overflow operations as xor/and (PR #69191)

[Simon Pilgrim via llvm-commits]

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@@ -9854,6 +9854,27 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
       SDValue ZeroOverFlow = getConstant(0, DL, VTList.VTs[1]);
       return getNode(ISD::MERGE_VALUES, DL, VTList, {N1, ZeroOverFlow}, Flags);
     }
+
+    if (VTList.VTs[0].isVector() &&
+        VTList.VTs[0].getVectorElementType() == MVT::i1 &&
+        VTList.VTs[1].getVectorElementType() == MVT::i1) {
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RKSimon wrote:

Mainly because all other add/sub/sat cases did

https://github.com/llvm/llvm-project/pull/69191