[llvm] [BOLT][RISCV] Implement getCalleeSavedRegs (PR #69161)

[Job Noorman via llvm-commits]

https://github.com/mtvec created https://github.com/llvm/llvm-project/pull/69161

The main reason for implementing this now is to ensure the `assume=abi.test` test passes on RISC-V. Since it uses `--indirect-call-promotion=all`, it requires some support for register analysis on the target.

Further testing and implementation of register/frame analysis on RISC-V will come later.

>From 65edb7cd34d5df7f6bf2ad7c52c56afab02394df Mon Sep 17 00:00:00 2001
From: Job Noorman <jnoorman at igalia.com>
Date: Mon, 16 Oct 2023 10:32:02 +0200
Subject: [PATCH] [BOLT][RISCV] Implement getCalleeSavedRegs

The main reason for implementing this now is to ensure the
`assume=abi.test` test passes on RISC-V. Since it uses
`--indirect-call-promotion=all`, it requires some support for register
analysis on the target.

Further testing and implementation of register/frame analysis on RISC-V
will come later.
---
 bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
index 64bd318e06e8709..85855fbf3ab97f4 100644
--- a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
+++ b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
@@ -42,6 +42,22 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
                                  *RISCVExprB.getSubExpr(), Comp);
   }
 
+  void getCalleeSavedRegs(BitVector &Regs) const override {
+    Regs |= getAliases(RISCV::X2);
+    Regs |= getAliases(RISCV::X8);
+    Regs |= getAliases(RISCV::X9);
+    Regs |= getAliases(RISCV::X18);
+    Regs |= getAliases(RISCV::X19);
+    Regs |= getAliases(RISCV::X20);
+    Regs |= getAliases(RISCV::X21);
+    Regs |= getAliases(RISCV::X22);
+    Regs |= getAliases(RISCV::X23);
+    Regs |= getAliases(RISCV::X24);
+    Regs |= getAliases(RISCV::X25);
+    Regs |= getAliases(RISCV::X26);
+    Regs |= getAliases(RISCV::X27);
+  }
+
   bool shouldRecordCodeRelocation(uint64_t RelType) const override {
     switch (RelType) {
     case ELF::R_RISCV_JAL: