[llvm] Improve selection of conditional branch on amdgcn.ballot!=0 condition in SelectionDAG. (PR #68714)

via llvm-commits llvm-commits at lists.llvm.org
Sun Oct 15 02:00:27 PDT 2023


github-actions[bot] wrote:


<!--LLVM CODE FORMAT COMMENT: {clang-format}-->

:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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git-clang-format --diff 12a4757b0fa25baac853498671a34e2f34f92b80 4429535711565c803420cc90ead993763e5b9a62 -- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 35576dec3dd0..b0defa3e0b19 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -2300,7 +2300,7 @@ void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
   bool Negate = false;
 
   if (Cond.getOpcode() == ISD::SETCC &&
-      Cond->getOperand(0)->getOpcode() == AMDGPUISD::SETCC) {   
+      Cond->getOperand(0)->getOpcode() == AMDGPUISD::SETCC) {
     auto CC = cast<CondCodeSDNode>(Cond->getOperand(2))->get();
     auto *CRHS = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
     if ((CC == ISD::SETEQ || CC == ISD::SETNE) && CRHS && CRHS->isZero()) {

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https://github.com/llvm/llvm-project/pull/68714


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