[llvm] RegisterCoalescer: Relax assert for super register def rematerialization (PR #69088)
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Sat Oct 14 19:51:04 PDT 2023
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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git-clang-format --diff 2dc6579f6fb12470559a68886c2a4aecaa8495dd 19c142e1f6b2214716d7145c07c7a04845b17a92 -- llvm/lib/CodeGen/RegisterCoalescer.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 78c5ccde5..9858482cd 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1437,9 +1437,8 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
(DefSubIdx &&
((TRI->getSubReg(MO.getReg(), DefSubIdx) ==
MCRegister((unsigned)NewMI.getOperand(0).getReg())) ||
- TRI->isSubRegisterEq(NewMI.getOperand(0).getReg(), MO.getReg())
- )))
- );
+ TRI->isSubRegisterEq(NewMI.getOperand(0).getReg(),
+ MO.getReg())))));
NewMIImplDefs.push_back(MO.getReg().asMCReg());
} else {
assert(MO.getReg() == NewMI.getOperand(0).getReg());
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https://github.com/llvm/llvm-project/pull/69088
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