[llvm] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)

[Kito Cheng via llvm-commits]

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@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
           CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
     return;
 
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
+  if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
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kito-cheng wrote:

> I believe that setting up this memory and initializing the SCS reg would fall under activate the use of Zicfiss..., but I could be wrong.

That suppose initialize SCS register by kernel, more precisely is user space will invoke some prctl system call to enable SCS and the kernel will allocate SCS page and then initialize the SCS register then back to user space.

https://github.com/llvm/llvm-project/pull/68075