[llvm] [RISCV] Improve cleanup phase of RISCV Insert VSETVLI pass (PR #67144)

[Ju-Zhe Zhong via llvm-commits]

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@@ -834,8 +834,7 @@ define <vscale x 2 x i32> @pre_lmul(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y
 ; CHECK-LABEL: pre_lmul:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vadd.vv v8, v8, v9
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zhongjuzhe wrote:

It seems incorrect.

According to the LLVM IR, is should be processing VLMAX number of element of SEW = 64, LMUL = 1.

Suppose RVV VLEN = 128bit:

SEW = 64, LMUL = 1, the vsetvlmax output should be 2 elements.
SEW = 32, LMUL = 1, the vsetvlmax output should be 4 elements.
According to LLVM IR:
%vl = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 %vl)

%vl output should be 2 elements, then later "vadd" should be processing 2 elements.

Here the new assembly after this patch is:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v9
The "vadd.vv" is processing 4 elements.

https://github.com/llvm/llvm-project/pull/67144