[llvm] c40902c - [AMDGPU] Use llvm::endianness::little (NFC)

[Kazu Hirata via llvm-commits]

Author: Kazu Hirata
Date: 2023-10-12T21:02:02-07:00
New Revision: c40902c41c007ae42ab9a1e80008d81ec4eec24f

URL: https://github.com/llvm/llvm-project/commit/c40902c41c007ae42ab9a1e80008d81ec4eec24f
DIFF: https://github.com/llvm/llvm-project/commit/c40902c41c007ae42ab9a1e80008d81ec4eec24f.diff

LOG: [AMDGPU] Use llvm::endianness::little (NFC)

Note that llvm::support::endianness has been renamed to
llvm::endianness.  This patch replaces support::endianness::little
with llvm::endianness::little.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index d93f747bf6f0a64..88c1668f62800aa 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -414,7 +414,7 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
     if (Desc.operands()[i].OperandType == AMDGPU::OPERAND_REG_IMM_FP64)
       Imm = Hi_32(Imm);
 
-    support::endian::write<uint32_t>(CB, Imm, support::endianness::little);
+    support::endian::write<uint32_t>(CB, Imm, llvm::endianness::little);
 
     // Only one literal value allowed
     break;