[llvm] 37441f1 - [PhaseOrdering] Add test for switch with different GEP types (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-10-12T14:01:58+02:00
New Revision: 37441f1ae66e6ca5380b338454db736173ff9fcd

URL: https://github.com/llvm/llvm-project/commit/37441f1ae66e6ca5380b338454db736173ff9fcd
DIFF: https://github.com/llvm/llvm-project/commit/37441f1ae66e6ca5380b338454db736173ff9fcd.diff

LOG: [PhaseOrdering] Add test for switch with different GEP types (NFC)

Added: 
    llvm/test/Transforms/PhaseOrdering/switch_different_gep_types.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/PhaseOrdering/switch_
diff erent_gep_types.ll b/llvm/test/Transforms/PhaseOrdering/switch_
diff erent_gep_types.ll
new file mode 100644
index 000000000000000..29a3fc03f4663ee
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/switch_
diff erent_gep_types.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
+; RUN: opt -S -passes='default<O1>' < %s | FileCheck %s
+; RUN: opt -S -passes='default<O2>' < %s | FileCheck %s
+; RUN: opt -S -passes='default<O3>' < %s | FileCheck %s
+
+%"OpKind::Zero" = type { [1 x i32], i32 }
+%"OpKind::One" = type { [1 x i32], i32, i16, [1 x i16] }
+%"OpKind::Two" = type { [1 x i32], i32, i16, i16 }
+%"OpKind::Three" = type { [1 x i32], i32, i16, i16, i16, [1 x i16] }
+
+; FIXME: The switch should be optimized away.
+define i32 @test(ptr %ptr) {
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: ptr nocapture readonly [[PTR:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[T:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT:    switch i32 [[T]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT:    i32 0, label [[BB4:%.*]]
+; CHECK-NEXT:    i32 1, label [[BB5:%.*]]
+; CHECK-NEXT:    i32 2, label [[BB6:%.*]]
+; CHECK-NEXT:    i32 3, label [[BB7:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       default:
+; CHECK-NEXT:    unreachable
+; CHECK:       bb4:
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds %"OpKind::Zero", ptr [[PTR]], i64 0, i32 1
+; CHECK-NEXT:    br label [[EXIT:%.*]]
+; CHECK:       bb5:
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds %"OpKind::One", ptr [[PTR]], i64 0, i32 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       bb6:
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds %"OpKind::Two", ptr [[PTR]], i64 0, i32 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       bb7:
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds %"OpKind::Three", ptr [[PTR]], i64 0, i32 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    [[PHI:%.*]] = phi ptr [ [[GEP3]], [[BB7]] ], [ [[GEP2]], [[BB6]] ], [ [[GEP1]], [[BB5]] ], [ [[GEP0]], [[BB4]] ]
+; CHECK-NEXT:    [[RET:%.*]] = load i32, ptr [[PHI]], align 4
+; CHECK-NEXT:    ret i32 [[RET]]
+;
+start:
+  %t = load i32, ptr %ptr, align 4
+  switch i32 %t, label %default [
+  i32 0, label %bb4
+  i32 1, label %bb5
+  i32 2, label %bb6
+  i32 3, label %bb7
+  ]
+
+default:
+  unreachable
+
+bb4:
+  %gep0 = getelementptr inbounds %"OpKind::Zero", ptr %ptr, i64 0, i32 1
+  br label %exit
+
+bb5:
+  %gep1 = getelementptr inbounds %"OpKind::One", ptr %ptr, i64 0, i32 1
+  br label %exit
+
+bb6:
+  %gep2 = getelementptr inbounds %"OpKind::Two", ptr %ptr, i64 0, i32 1
+  br label %exit
+
+bb7:
+  %gep3 = getelementptr inbounds %"OpKind::Three", ptr %ptr, i64 0, i32 1
+  br label %exit
+
+exit:
+  %phi = phi ptr [ %gep3, %bb7 ], [ %gep2, %bb6 ], [ %gep1, %bb5 ], [ %gep0, %bb4 ]
+  %ret = load i32, ptr %phi, align 4
+  ret i32 %ret
+}
+