[llvm] [AMDGPU][GlobalISel] Expand SGPR S1 exts into G_SELECT (PR #68858)

via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 12 04:26:53 PDT 2023


github-actions[bot] wrote:


<!--LLVM CODE FORMAT COMMENT: {clang-format}-->

:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 9dd15f7486a30c4269b183f72c13006eb8c929f4 d1959547f5621475fce4979450de7b0152a4ae80 -- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index b81256aaff58..20d950c1404c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2585,7 +2585,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
       MRI.setRegBank(True, AMDGPU::SGPRRegBank);
 
       // Extend to S16/S32, but keep it at S32 for S64 SelType.
-      Register SrcExt = B.buildZExt(SelType != S64 ? SelType : S32, SrcReg).getReg(0);
+      Register SrcExt =
+          B.buildZExt(SelType != S64 ? SelType : S32, SrcReg).getReg(0);
       MRI.setRegBank(SrcExt, AMDGPU::SGPRRegBank);
 
       B.buildSelect(DstReg, SrcExt, True, False);

``````````

</details>


https://github.com/llvm/llvm-project/pull/68858


More information about the llvm-commits mailing list