[llvm] feat: fix big endian shuffle vector miscompile (PR #68673)
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Thu Oct 12 01:37:03 PDT 2023
https://github.com/hstk30-hw updated https://github.com/llvm/llvm-project/pull/68673
>From ec74c1eda0f4f2fb96a595ed82e3b029c2b0317b Mon Sep 17 00:00:00 2001
From: hstk30-hw <hanwei62 at huawei.com>
Date: Tue, 10 Oct 2023 16:31:55 +0800
Subject: [PATCH] feat: fix big endian shuffle vector miscompile
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 14 +++++++++++---
llvm/test/CodeGen/AArch64/aarch64-load-ext.ll | 3 +--
.../CodeGen/AArch64/fix-shuffle-vector-be-rev.ll | 16 ++++++++++++++++
llvm/test/CodeGen/AArch64/zext-to-tbl.ll | 4 ----
4 files changed, 28 insertions(+), 9 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/fix-shuffle-vector-be-rev.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ac1ca04e15046b7..7050e70abef938c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10862,7 +10862,11 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
if (SrcEltTy == SmallestEltTy)
continue;
assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
- Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
+ if (DAG.getDataLayout().isBigEndian()) {
+ Src.ShuffleVec = DAG.getNode(AArch64ISD::NVCAST, dl, ShuffleVT, Src.ShuffleVec);
+ } else {
+ Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
+ }
Src.WindowScale =
SrcEltTy.getFixedSizeInBits() / SmallestEltTy.getFixedSizeInBits();
Src.WindowBase *= Src.WindowScale;
@@ -10914,8 +10918,12 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
ShuffleOps[1], Mask);
- SDValue V = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
-
+ SDValue V;
+ if (DAG.getDataLayout().isBigEndian()) {
+ SDValue V = DAG.getNode(AArch64ISD::NVCAST, dl, VT, Shuffle);
+ } else {
+ SDValue V = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
+ }
LLVM_DEBUG(dbgs() << "Reshuffle, creating node: "; Shuffle.dump();
dbgs() << "Reshuffle, creating node: "; V.dump(););
diff --git a/llvm/test/CodeGen/AArch64/aarch64-load-ext.ll b/llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
index cc7dffc497495a0..9911dcd0fc97abd 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
@@ -140,7 +140,6 @@ define <3 x i32> @fsext_v3i32(ptr %a) {
; CHECK-BE-NEXT: ldr s0, [x0]
; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
; CHECK-BE-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-BE-NEXT: rev16 v0.8b, v0.8b
; CHECK-BE-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-BE-NEXT: shl v0.4s, v0.4s, #24
; CHECK-BE-NEXT: sshr v0.4s, v0.4s, #24
@@ -284,7 +283,6 @@ define <3 x i16> @fsext_v3i16(ptr %a) {
; CHECK-BE-NEXT: ldr s0, [x0]
; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
; CHECK-BE-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-BE-NEXT: rev16 v0.8b, v0.8b
; CHECK-BE-NEXT: shl v0.4h, v0.4h, #8
; CHECK-BE-NEXT: sshr v0.4h, v0.4h, #8
; CHECK-BE-NEXT: rev64 v0.4h, v0.4h
@@ -447,6 +445,7 @@ define <4 x i8> @bitcast(i32 %0) {
; CHECK-BE-NEXT: fmov s0, w0
; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
; CHECK-BE-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-BE-NEXT: rev16 v0.8b, v0.8b
; CHECK-BE-NEXT: rev64 v0.8b, v0.8b
; CHECK-BE-NEXT: ret
%2 = bitcast i32 %0 to <4 x i8>
diff --git a/llvm/test/CodeGen/AArch64/fix-shuffle-vector-be-rev.ll b/llvm/test/CodeGen/AArch64/fix-shuffle-vector-be-rev.ll
new file mode 100644
index 000000000000000..fce61eece5bd217
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fix-shuffle-vector-be-rev.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=aarch64_be | FileCheck %s
+
+
+ define <4 x i1> @insert_rev_for_reconstructshuffle(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+; CHECK-LABEL: insert_rev_for_reconstructshuffle:
+; CHECK: zip2 v[[V1:[0-9]+]].8b, v[[V2:[0-9]+]].8b, v[[V3:[0-9]+]].8b
+; CHECK-NOT: rev16
+; CHECK-NOT: rev16
+ %tmp1 = load <16 x i8>, <16 x i8>* %A
+ %tmp2 = load <16 x i8>, <16 x i8>* %B
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ %tmp4 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
+ %tmp5 = icmp eq <4 x i8> %tmp3, %tmp4
+ %tmp6 = freeze <4 x i1> %tmp5
+ ret <4 x i1> %tmp6
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/AArch64/zext-to-tbl.ll b/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
index f24abb568400099..a2529723e1d95ca 100644
--- a/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
+++ b/llvm/test/CodeGen/AArch64/zext-to-tbl.ll
@@ -1345,10 +1345,6 @@ define void @zext_v16i4_to_v16i32_in_loop(ptr %src, ptr %dst) {
; CHECK-BE-NEXT: zip1 v1.8b, v1.8b, v0.8b
; CHECK-BE-NEXT: zip2 v4.8b, v2.8b, v0.8b
; CHECK-BE-NEXT: zip1 v2.8b, v2.8b, v0.8b
-; CHECK-BE-NEXT: rev16 v3.8b, v3.8b
-; CHECK-BE-NEXT: rev16 v1.8b, v1.8b
-; CHECK-BE-NEXT: rev16 v4.8b, v4.8b
-; CHECK-BE-NEXT: rev16 v2.8b, v2.8b
; CHECK-BE-NEXT: ushll v3.4s, v3.4h, #0
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-BE-NEXT: and v3.16b, v3.16b, v0.16b
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