[llvm] 127ed9a - [PowerPC] Use zext instead of anyext in custom and combine (#68784)
via llvm-commits
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Thu Oct 12 00:32:22 PDT 2023
Author: Nikita Popov
Date: 2023-10-12T09:32:17+02:00
New Revision: 127ed9ae266ead58aa525f74f4c86841f6674793
URL: https://github.com/llvm/llvm-project/commit/127ed9ae266ead58aa525f74f4c86841f6674793
DIFF: https://github.com/llvm/llvm-project/commit/127ed9ae266ead58aa525f74f4c86841f6674793.diff
LOG: [PowerPC] Use zext instead of anyext in custom and combine (#68784)
This custom combine currently converts `and(anyext(x),c)` into
`anyext(and(x,c))`. This is not correct, because the original expression
guaranteed that the high bits are zero, while the new one sets them to
undef.
Emit `zext(and(x,c))` instead.
Fixes https://github.com/llvm/llvm-project/issues/68783.
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/and-extend-combine.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index c6257dcdf76f633..5e0c2d62f5a9cb5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15588,7 +15588,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
break;
SDValue ConstOp = DAG.getConstant(Imm, dl, MVT::i32);
SDValue NarrowAnd = DAG.getNode(ISD::AND, dl, MVT::i32, NarrowOp, ConstOp);
- return DAG.getAnyExtOrTrunc(NarrowAnd, dl, N->getValueType(0));
+ return DAG.getZExtOrTrunc(NarrowAnd, dl, N->getValueType(0));
}
case ISD::SHL:
return combineSHL(N, DCI);
diff --git a/llvm/test/CodeGen/PowerPC/and-extend-combine.ll b/llvm/test/CodeGen/PowerPC/and-extend-combine.ll
index 11f83ccc6806d0d..0b30d48912dc374 100644
--- a/llvm/test/CodeGen/PowerPC/and-extend-combine.ll
+++ b/llvm/test/CodeGen/PowerPC/and-extend-combine.ll
@@ -23,11 +23,12 @@ bb:
ret ptr %i8
}
-; FIXME: This is a miscompile.
define void @pr68783(i32 %x, ptr %p) {
; CHECK-LABEL: pr68783:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm r3, r3, 31, 24, 31
+; CHECK-NEXT: li r5, 0
+; CHECK-NEXT: sth r5, 4(r4)
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
%lshr = lshr i32 %x, 1
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