[llvm] [IR] Add intrinsics to represent complex multiply and divide operations (PR #68742)

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git-clang-format --diff d4ae7ee662d2f318c0e4105c674e0634733b48eb bcd640cbdccbe58c1c301502ab8b93fdbd6cb04b -- llvm/include/llvm/CodeGen/ExpandComplex.h llvm/lib/CodeGen/ExpandComplex.cpp llvm/include/llvm/CodeGen/ISDOpcodes.h llvm/include/llvm/CodeGen/Passes.h llvm/include/llvm/CodeGen/TargetLowering.h llvm/include/llvm/IR/IRBuilder.h llvm/include/llvm/InitializePasses.h llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp llvm/lib/CodeGen/TargetPassConfig.cpp llvm/lib/IR/IRBuilder.cpp llvm/lib/IR/Verifier.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86ISelLowering.h
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diff --git a/llvm/lib/CodeGen/ExpandComplex.cpp b/llvm/lib/CodeGen/ExpandComplex.cpp
index 253de368cc7d..51233eb48bd1 100644
--- a/llvm/lib/CodeGen/ExpandComplex.cpp
+++ b/llvm/lib/CodeGen/ExpandComplex.cpp
@@ -123,7 +123,7 @@ bool expandComplexInstruction(IntrinsicInst *CI, const TargetLowering *TLI,
       // All we need to do is move the integer to a vector register, without any
       // other munging.
       uint64_t Width =
-        ComplexVectorTy->getPrimitiveSizeInBits().getFixedValue();
+          ComplexVectorTy->getPrimitiveSizeInBits().getFixedValue();
       Type *IntegerTy = Builder.getIntNTy(Width);
       FunctionCallee Func = CI->getModule()->getOrInsertFunction(
           Name, IntegerTy, FloatTy, FloatTy, FloatTy, FloatTy);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 75007a03573e..72fbef1ae5f6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -513,7 +513,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
     return "stackmap";
   case ISD::PATCHPOINT:
     return "patchpoint";
-  case ISD::COMPLEX_MUL:                return "complex_mul";
+  case ISD::COMPLEX_MUL:
+    return "complex_mul";
 
     // Vector Predication
 #define BEGIN_REGISTER_VP_SDNODE(SDID, LEGALARG, NAME, ...)                    \
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index c453c944d37e..0391c20cfb35 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -5972,7 +5972,7 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
     Type *ArgTy = Call.getArgOperand(0)->getType();
     FixedVectorType *VectorTy = dyn_cast<FixedVectorType>(ArgTy);
     Check(VectorTy && VectorTy->getNumElements() % 2 == 0 &&
-            VectorTy->getElementType()->isFloatingPointTy(),
+              VectorTy->getElementType()->isFloatingPointTy(),
           "complex intrinsic must use an even-length vector of floating-point "
           "types",
           &Call);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1ebbc9fca345..b0640b6eb07d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2555,7 +2555,7 @@ X86TargetLowering::getComplexReturnABI(Type *ScalarFloatTy) const {
   // 32 and 64-bit ABIs).
   if (Subtarget.isOSWindows()) {
     unsigned FloatSize =
-      ScalarFloatTy->getPrimitiveSizeInBits().getFixedValue();
+        ScalarFloatTy->getPrimitiveSizeInBits().getFixedValue();
     if (FloatSize <= 32) {
       return ComplexABI::Integer;
     } else {
@@ -2576,7 +2576,7 @@ X86TargetLowering::getComplexReturnABI(Type *ScalarFloatTy) const {
     // single vector in xmm0; double and x86-fp80 (by special case) return two
     // values; and larger types than x86-fp80 (i.e., fp128) returns via memory.
     unsigned FloatSize =
-      ScalarFloatTy->getPrimitiveSizeInBits().getFixedValue();
+        ScalarFloatTy->getPrimitiveSizeInBits().getFixedValue();
     if (FloatSize <= 32) {
       return ComplexABI::Vector;
     } else if (FloatSize <= 80) {
@@ -32022,7 +32022,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::ADDRSPACECAST:      return LowerADDRSPACECAST(Op, DAG);
   case X86ISD::CVTPS2PH:        return LowerCVTPS2PH(Op, DAG);
   case ISD::PREFETCH:           return LowerPREFETCH(Op, Subtarget, DAG);
-  case ISD::COMPLEX_MUL:        return LowerComplexMUL(Op, DAG, Subtarget);
+  case ISD::COMPLEX_MUL:
+    return LowerComplexMUL(Op, DAG, Subtarget);
   }
 }
 
@@ -33129,8 +33130,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
     MVT VT = N->getSimpleValueType(0);
     // FIXME: (COMPLEX_MUL v2f16, v2f16) should be lowered to VFMULCSH but we
     // mix the v2f16 and v4f16 here.
-    assert((VT == MVT::v2f32 || VT == MVT::v2f16 ||
-           VT == MVT::v4f16) && "Unexpected Value type of COMPLEX_MUL!");
+    assert((VT == MVT::v2f32 || VT == MVT::v2f16 || VT == MVT::v4f16) &&
+           "Unexpected Value type of COMPLEX_MUL!");
     MVT WideVT =
         VT.getVectorElementType() == MVT::f16 ? MVT::v8f16 : MVT::v4f32;
     SmallVector<SDValue, 4> Ops(VT == MVT::v2f16 ? 4 : 2, DAG.getUNDEF(VT));

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https://github.com/llvm/llvm-project/pull/68742