[llvm] [SVE][InstCombine] Delete redundante sel instructions with ptrue (PR #68463)

[via llvm-commits]

https://github.com/vfdff updated https://github.com/llvm/llvm-project/pull/68463

>From 1f73f7718ec8126a3218c3f3afbe74a52862bdee Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Fri, 6 Oct 2023 21:54:36 -0400
Subject: [PATCH 1/2] [SVE][InstCombine] Precommit tests for select + ptrue

---
 .../InstCombine/AArch64/sve-intrinsic-sel.ll         | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
index b0f059c9de605e1..0d0c3b9892758e1 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
@@ -12,6 +12,18 @@ define <vscale x 4 x i32> @replace_sel_intrinsic(<vscale x 4 x i1> %p, <vscale x
   ret <vscale x 4 x i32> %1
 }
 
+define <vscale x 4 x i32> @sel_ptrue(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: @sel_ptrue(
+; CHECK-NEXT:    [[PRED:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+; CHECK-NEXT:    [[RES:%.*]] = select <vscale x 4 x i1> [[PRED]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[RES]]
+;
+  %pred = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+  %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %pred, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
+  ret <vscale x 4 x i32> %res
+}
+
+declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
 declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
 
 attributes #0 = { "target-features"="+sve" }

>From 3a7485759609919991004a9aed559cc36f41efb2 Mon Sep 17 00:00:00 2001
From: zhongyunde 00443407 <zhongyunde at huawei.com>
Date: Wed, 27 Sep 2023 22:42:43 -0400
Subject: [PATCH 2/2] [SVE][InstCombine] Delete redundante sel instructions
 with ptrue

svsel(pture, x, y) => x. depend on D121792
---
 llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp     | 7 +++++++
 .../Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll    | 4 +---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index cded28054f59259..70bdb29ffcb13c3 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -800,6 +800,13 @@ instCombineConvertFromSVBool(InstCombiner &IC, IntrinsicInst &II) {
 
 static std::optional<Instruction *> instCombineSVESel(InstCombiner &IC,
                                                       IntrinsicInst &II) {
+  // svsel(ptrue, x, y) => x
+  auto *OpPredicate = II.getOperand(0);
+  if (match(OpPredicate, m_Intrinsic<Intrinsic::aarch64_sve_ptrue>(
+                             m_ConstantInt<AArch64SVEPredPattern::all>()))) {
+    return IC.replaceInstUsesWith(II, II.getOperand(1));
+  }
+
   auto Select = IC.Builder.CreateSelect(II.getOperand(0), II.getOperand(1),
                                         II.getOperand(2));
   return IC.replaceInstUsesWith(II, Select);
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
index 0d0c3b9892758e1..c6f08ce82882664 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
@@ -14,9 +14,7 @@ define <vscale x 4 x i32> @replace_sel_intrinsic(<vscale x 4 x i1> %p, <vscale x
 
 define <vscale x 4 x i32> @sel_ptrue(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
 ; CHECK-LABEL: @sel_ptrue(
-; CHECK-NEXT:    [[PRED:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
-; CHECK-NEXT:    [[RES:%.*]] = select <vscale x 4 x i1> [[PRED]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]
-; CHECK-NEXT:    ret <vscale x 4 x i32> [[RES]]
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[A:%.*]]
 ;
   %pred = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
   %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %pred, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)