[llvm] [AMDGPU] Save and restore SCC using only 32-bit SGPR. (PR #68367)

[Pierre van Houtryve via llvm-commits]

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@@ -1084,13 +1083,19 @@ void SIFixSGPRCopies::fixSCCCopies(MachineFunction &MF) {
       Register SrcReg = MI.getOperand(1).getReg();
       Register DstReg = MI.getOperand(0).getReg();
       if (SrcReg == AMDGPU::SCC) {
-        Register SCCCopy = MRI->createVirtualRegister(
-            TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID));
+        const TargetRegisterClass *DstRC =
+            TRI->getRegClassForOperandReg(*MRI, MI.getOperand(0));
+        assert((TRI->getRegSizeInBits(*DstRC) == 64 ||
+                TRI->getRegSizeInBits(*DstRC) == 32) &&
+               "Expected SCC dst to be 64 or 32 bits");
+        bool IsDst32Bit = TRI->getRegSizeInBits(*DstRC) == 32;
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Pierre-vh wrote:

Save `TRI->getRegSizeInBits(*DstRC)` in a variable to reduce repetition, same below.

https://github.com/llvm/llvm-project/pull/68367