[llvm] [AMDGPU] Save and restore SCC using only 32-bit SGPR. (PR #68367)

[Pierre van Houtryve via llvm-commits]

================
@@ -1084,13 +1083,19 @@ void SIFixSGPRCopies::fixSCCCopies(MachineFunction &MF) {
       Register SrcReg = MI.getOperand(1).getReg();
       Register DstReg = MI.getOperand(0).getReg();
       if (SrcReg == AMDGPU::SCC) {
-        Register SCCCopy = MRI->createVirtualRegister(
-            TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID));
+        const TargetRegisterClass *DstRC =
+            TRI->getRegClassForOperandReg(*MRI, MI.getOperand(0));
+        assert((TRI->getRegSizeInBits(*DstRC) == 64 ||
+                TRI->getRegSizeInBits(*DstRC) == 32) &&
+               "Expected SCC dst to be 64 or 32 bits");
+        bool IsDst32Bit = TRI->getRegSizeInBits(*DstRC) == 32;
+        Register SCCCopy =
+            IsDst32Bit ? MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass)
+                       : MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
----------------
Pierre-vh wrote:

I think you can just do 
```
MRI->createVirtualRegister(IsDst32Bit ? &AMDGPU::SReg_32RegClass : &AMDGPU::SReg_64RegClass)
```

https://github.com/llvm/llvm-project/pull/68367