[llvm] [RISCV] Replace PostRAScheduler with PostMachineScheduler (PR #68696)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 10 05:14:25 PDT 2023
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/68696
Just like what other targets have done.
And this will make DAG mutations like MacroFusion take effect.
This PR is stacked on #68692.
>From 94de10e9dfd6c7ab1027817d14db45afc3957380 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 10 Oct 2023 19:33:06 +0800
Subject: [PATCH 1/2] [RISCV] Make PostRAScheduler a target feature
This is what AArch64 has done in https://reviews.llvm.org/D20762.
Tests are added in macro fusion tests, which uncover a bug that
DAG mutations don't take effect.
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +++
llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 ++++
llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll | 15 +++++++++++++++
3 files changed, 22 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3d3486b7fa89563..548579173f0ede4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -902,6 +902,9 @@ def FeatureUnalignedVectorMem
"true", "Has reasonably performant unaligned vector "
"loads and stores">;
+def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
+ "UsePostRAScheduler", "true", "Schedule again after register allocation">;
+
def TuneNoOptimizedZeroStrideLoad
: SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
"false", "Hasn't optimized (perform fewer memory operations)"
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 027d32d54160793..6b915e61c136086 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -107,6 +107,10 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
}
bool enableMachineScheduler() const override { return true; }
+ bool enablePostRAScheduler() const override {
+ return getSchedModel().PostRAScheduler || UsePostRAScheduler;
+ }
+
Align getPrefFunctionAlignment() const {
return Align(TuneInfo->PrefFunctionAlignment);
}
diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
index 7de0fd050d65867..18d1449d0e2e837 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
@@ -3,6 +3,8 @@
;RUN: | FileCheck %s --check-prefix=NOFUSION
;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion -mcpu=sifive-u74 \
;RUN: -target-abi=lp64f | FileCheck %s --check-prefix=FUSION
+;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion,+use-postra-scheduler -mcpu=sifive-u74 \
+;RUN: -target-abi=lp64f | FileCheck %s --check-prefixes=FUSION-POSTRA
@.str = private constant [4 x i8] c"%f\0A\00", align 1
@@ -20,6 +22,13 @@ define void @foo(i32 signext %0, i32 signext %1) {
; FUSION-NEXT: lui a0, %hi(.L.str)
; FUSION-NEXT: addi a0, a0, %lo(.L.str)
; FUSION-NEXT: tail bar at plt
+;
+; FUSION-POSTRA-LABEL: foo:
+; FUSION-POSTRA: # %bb.0:
+; FUSION-POSTRA-NEXT: lui a0, %hi(.L.str)
+; FUSION-POSTRA-NEXT: fcvt.s.w fa0, a1
+; FUSION-POSTRA-NEXT: addi a0, a0, %lo(.L.str)
+; FUSION-POSTRA-NEXT: tail bar at plt
%3 = sitofp i32 %1 to float
tail call void @bar(ptr @.str, float %3)
ret void
@@ -40,5 +49,11 @@ define i32 @test_matint() {
; FUSION-NEXT: lui a0, 1
; FUSION-NEXT: addiw a0, a0, -2048
; FUSION-NEXT: ret
+;
+; FUSION-POSTRA-LABEL: test_matint:
+; FUSION-POSTRA: # %bb.0:
+; FUSION-POSTRA-NEXT: lui a0, 1
+; FUSION-POSTRA-NEXT: addiw a0, a0, -2048
+; FUSION-POSTRA-NEXT: ret
ret i32 2048
}
>From 4751275c055c96e56d8b47d0ac251d69a22583aa Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 10 Oct 2023 20:12:20 +0800
Subject: [PATCH 2/2] [RISCV] Replace PostRAScheduler with PostMachineScheduler
Just like what other targets have done.
And this will make DAG mutations like MacroFusion take effect.
---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 ++
llvm/test/CodeGen/RISCV/O3-pipeline.ll | 2 +-
llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll | 2 +-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 1281528ea511a4d..651d24bae57263d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -248,6 +248,8 @@ class RISCVPassConfig : public TargetPassConfig {
public:
RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {
+ if (TM.getOptLevel() != CodeGenOptLevel::None)
+ substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
setEnableSinkAndFold(EnableSinkFold);
}
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 277951782ce5ccb..30b6e1e541394d0 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -159,7 +159,7 @@
; CHECK-NEXT: Insert KCFI indirect call checks
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
-; CHECK-NEXT: Post RA top-down list latency scheduler
+; CHECK-NEXT: PostRA Machine Instruction Scheduler
; CHECK-NEXT: Analyze Machine Code For Garbage Collection
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: MachinePostDominator Tree Construction
diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
index 18d1449d0e2e837..498e6cf23ba3495 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
@@ -25,8 +25,8 @@ define void @foo(i32 signext %0, i32 signext %1) {
;
; FUSION-POSTRA-LABEL: foo:
; FUSION-POSTRA: # %bb.0:
-; FUSION-POSTRA-NEXT: lui a0, %hi(.L.str)
; FUSION-POSTRA-NEXT: fcvt.s.w fa0, a1
+; FUSION-POSTRA-NEXT: lui a0, %hi(.L.str)
; FUSION-POSTRA-NEXT: addi a0, a0, %lo(.L.str)
; FUSION-POSTRA-NEXT: tail bar at plt
%3 = sitofp i32 %1 to float
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