[llvm] [AMDGPU][IGLP] SingleWaveOpt: Cache DSW Counters from PreRA (PR #67759)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 10 02:50:08 PDT 2023
================
@@ -1105,14 +1112,20 @@ class MFMASmallGemmSingleWaveOpt final : public IGLPStrategy {
}
};
+static unsigned DSWCount = 0;
+static unsigned DSWWithPermCount = 0;
+static unsigned DSWWithSharedVMEMCount = 0;
+
void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
DenseMap<int, SUnitsToCandidateSGsMap> &SyncedInstrs,
- DenseMap<int, SmallVector<SchedGroup, 4>> &SyncedSchedGroups) {
+ DenseMap<int, SmallVector<SchedGroup, 4>> &SyncedSchedGroups,
+ bool IsPostRA) {
unsigned MFMACount = 0;
- unsigned DSWCount = 0;
- unsigned DSWWithPermCount = 0;
- unsigned DSWWithSharedVMEMCount = 0;
unsigned DSRCount = 0;
+
+ assert((IsPostRA ||
+ DSWCount == DSWWithPermCount == DSWWithSharedVMEMCount == 0) &&
----------------
mikaelholmen wrote:
Hi @jrbyrnes
I don't know this code at all, but gcc warned on this assert and suggested some paratheses, so it caught my eye.
Does it really check what the assert string says?
I think e.g. the assert passes if the counts are 1, 1, 0 but the string says all should be 0?
https://github.com/llvm/llvm-project/pull/67759
More information about the llvm-commits
mailing list