[llvm] [RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (PR #66659)

[Luke Lau via llvm-commits]

lukel97 wrote:

> > Have we arrived at a point where we just never reach isel with a VMV_S_X with a register class other than LMUL=1?
> 
> I think so. Any clean up you see resulting from that? Are there some pseudos we could delete, or are those still required by mca?

I tried this out and it looks like we can get rid of the pseudos. However because it no longer carries information about LMUL, if a vmv.s.x is the first instruction in a basic block then it now has an LMUL of 1 by default. This is fine on its own but we can end up with a VL toggle if subsequent instructions don't have the same SEW/LMUL ratio, e.g:

```diff
-; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
 ; CHECK-NEXT:    vmv.s.x v9, zero
-; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
```

I think we can remediate this by teaching RISCVInsertVSETVLI to mutate LMUL to match the next SEW/LMUL ratio, provided LMUL or the SEW/LMUL ratio aren't used. That way we end up with the same SEW/LMUL ratio in both and can keep VL intact. I'm working on a patch for this, will post it separately

https://github.com/llvm/llvm-project/pull/66659