[llvm] [VP][NFC] Add 32-bit test for VP (PR #68582)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 9 05:49:00 PDT 2023
https://github.com/LiqinWeng created https://github.com/llvm/llvm-project/pull/68582
None
>From 30684390779ca5c41c152cc2125a1f81f9c36020 Mon Sep 17 00:00:00 2001
From: "liqin.weng" <liqin.weng at spacemit.com>
Date: Mon, 9 Oct 2023 20:38:10 +0800
Subject: [PATCH] [VP][NFC] Add 32-bit test for VP
---
.../CodeGen/X86/expand-vp-fp-intrinsics.ll | 177 ++++++++++++
.../CodeGen/X86/expand-vp-int-intrinsics.ll | 268 ++++++++++++++++++
2 files changed, 445 insertions(+)
diff --git a/llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll b/llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll
index 55750be8bdca393..018b6c2d20f1eee 100644
--- a/llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/expand-vp-fp-intrinsics.ll
@@ -1,10 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512
define void @vp_fadd_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_fadd_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vaddps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_fadd_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: addps %xmm1, %xmm0
@@ -23,6 +31,13 @@ define void @vp_fadd_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp)
declare <4 x float> @llvm.vp.fadd.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define void @vp_fsub_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_fsub_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vsubps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_fsub_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: subps %xmm1, %xmm0
@@ -41,6 +56,13 @@ define void @vp_fsub_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp)
declare <4 x float> @llvm.vp.fsub.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define void @vp_fmul_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_fmul_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vmulps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_fmul_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: mulps %xmm1, %xmm0
@@ -59,6 +81,13 @@ define void @vp_fmul_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp)
declare <4 x float> @llvm.vp.fmul.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define void @vp_fdiv_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_fdiv_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vdivps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_fdiv_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: divps %xmm1, %xmm0
@@ -77,6 +106,48 @@ define void @vp_fdiv_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp)
declare <4 x float> @llvm.vp.fdiv.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define void @vp_frem_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_frem_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $80, %esp
+; X86-NEXT: vmovups %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: vextractps $2, %xmm1, {{[0-9]+}}(%esp)
+; X86-NEXT: vextractps $2, %xmm0, (%esp)
+; X86-NEXT: calll fmodf
+; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vextractps $1, %xmm0, (%esp)
+; X86-NEXT: calll fmodf
+; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vmovss %xmm0, (%esp)
+; X86-NEXT: calll fmodf
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vextractps $3, %xmm0, (%esp)
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: calll fmodf
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
+; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; X86-NEXT: vmovaps %xmm0, (%esi)
+; X86-NEXT: addl $80, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_frem_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: pushq %rbx
@@ -157,6 +228,13 @@ define void @vp_frem_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp)
declare <4 x float> @llvm.vp.frem.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define void @vp_fabs_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_fabs_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_fabs_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -188,6 +266,13 @@ define void @vp_fabs_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp)
declare <4 x float> @llvm.vp.fabs.v4f32(<4 x float>, <4 x i1>, i32)
define void @vp_sqrt_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_sqrt_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vsqrtps %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_sqrt_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: sqrtps %xmm0, %xmm0
@@ -206,6 +291,13 @@ define void @vp_sqrt_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp)
declare <4 x float> @llvm.vp.sqrt.v4f32(<4 x float>, <4 x i1>, i32)
define void @vp_fneg_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_fneg_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_fneg_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -237,6 +329,55 @@ define void @vp_fneg_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i32 %vp)
declare <4 x float> @llvm.vp.fneg.v4f32(<4 x float>, <4 x i1>, i32)
define void @vp_fma_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i4 %a5) nounwind {
+; X86-LABEL: vp_fma_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $84, %esp
+; X86-NEXT: vmovupd %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: vextractps $2, %xmm0, (%esp)
+; X86-NEXT: vshufpd {{.*#+}} xmm0 = xmm1[1,0]
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: calll fmaf
+; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vextractps $1, %xmm0, (%esp)
+; X86-NEXT: vmovshdup {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; X86-NEXT: # xmm0 = mem[1,1,3,3]
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: calll fmaf
+; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vmovss %xmm0, (%esp)
+; X86-NEXT: calll fmaf
+; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; X86-NEXT: vextractps $3, %xmm0, (%esp)
+; X86-NEXT: vpermilps $255, {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; X86-NEXT: # xmm0 = mem[3,3,3,3]
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: calll fmaf
+; X86-NEXT: fstps {{[0-9]+}}(%esp)
+; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
+; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; X86-NEXT: vmovaps %xmm0, (%esi)
+; X86-NEXT: addl $84, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_fma_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: pushq %rbx
@@ -372,6 +513,14 @@ define void @vp_fma_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i4 %a5) no
declare <4 x float> @llvm.vp.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, <4 x i1>, i32)
define void @vp_fmuladd_v4f32(<4 x float> %a0, <4 x float> %a1, ptr %out, i4 %a5) nounwind {
+; X86-LABEL: vp_fmuladd_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vmulps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vaddps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_fmuladd_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: mulps %xmm1, %xmm0
@@ -406,6 +555,13 @@ declare <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>
declare <4 x float> @llvm.vp.maxnum.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define <4 x float> @vfmax_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; X86-LABEL: vfmax_vv_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: vmaxps %xmm0, %xmm1, %xmm2
+; X86-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; X86-NEXT: retl
+;
; SSE-LABEL: vfmax_vv_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm1, %xmm2
@@ -443,6 +599,13 @@ define <4 x float> @vfmax_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m
declare <8 x float> @llvm.vp.maxnum.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
define <8 x float> @vfmax_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; X86-LABEL: vfmax_vv_v8f32:
+; X86: # %bb.0:
+; X86-NEXT: vmaxps %ymm0, %ymm1, %ymm2
+; X86-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
+; X86-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
+; X86-NEXT: retl
+;
; SSE-LABEL: vfmax_vv_v8f32:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm2, %xmm4
@@ -486,6 +649,13 @@ define <8 x float> @vfmax_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m
declare <4 x float> @llvm.vp.minnum.v4f32(<4 x float>, <4 x float>, <4 x i1>, i32)
define <4 x float> @vfmin_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 zeroext %evl) {
+; X86-LABEL: vfmin_vv_v4f32:
+; X86: # %bb.0:
+; X86-NEXT: vminps %xmm0, %xmm1, %xmm2
+; X86-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
+; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; X86-NEXT: retl
+;
; SSE-LABEL: vfmin_vv_v4f32:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm1, %xmm2
@@ -523,6 +693,13 @@ define <4 x float> @vfmin_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m
declare <8 x float> @llvm.vp.minnum.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
define <8 x float> @vfmin_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 zeroext %evl) {
+; X86-LABEL: vfmin_vv_v8f32:
+; X86: # %bb.0:
+; X86-NEXT: vminps %ymm0, %ymm1, %ymm2
+; X86-NEXT: vcmpunordps %ymm0, %ymm0, %ymm0
+; X86-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
+; X86-NEXT: retl
+;
; SSE-LABEL: vfmin_vv_v8f32:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm2, %xmm4
diff --git a/llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll b/llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
index c936bf720275243..f8a24542b0eb249 100644
--- a/llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
@@ -1,10 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512
define void @vp_add_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_add_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_add_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm1, %xmm0
@@ -23,6 +31,13 @@ define void @vp_add_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounw
declare <4 x i32> @llvm.vp.add.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_sub_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_sub_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpsubd %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_sub_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: psubd %xmm1, %xmm0
@@ -41,6 +56,13 @@ define void @vp_sub_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounw
declare <4 x i32> @llvm.vp.sub.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_mul_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_mul_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmulld %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_mul_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
@@ -65,6 +87,42 @@ define void @vp_mul_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounw
declare <4 x i32> @llvm.vp.mul.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_sdiv_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_sdiv_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm2
+; X86-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3]
+; X86-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
+; X86-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; X86-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-NEXT: vextractps $1, %xmm1, %ecx
+; X86-NEXT: vpextrd $1, %xmm0, %eax
+; X86-NEXT: cltd
+; X86-NEXT: idivl %ecx
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: vmovd %xmm1, %edi
+; X86-NEXT: vmovd %xmm0, %eax
+; X86-NEXT: cltd
+; X86-NEXT: idivl %edi
+; X86-NEXT: vmovd %eax, %xmm2
+; X86-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
+; X86-NEXT: vpextrd $2, %xmm1, %ecx
+; X86-NEXT: vpextrd $2, %xmm0, %eax
+; X86-NEXT: cltd
+; X86-NEXT: idivl %ecx
+; X86-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
+; X86-NEXT: vpextrd $3, %xmm1, %ecx
+; X86-NEXT: vpextrd $3, %xmm0, %eax
+; X86-NEXT: cltd
+; X86-NEXT: idivl %ecx
+; X86-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%esi)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_sdiv_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movd %esi, %xmm2
@@ -208,6 +266,42 @@ define void @vp_sdiv_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.sdiv.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_udiv_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_udiv_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm2
+; X86-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3]
+; X86-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
+; X86-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; X86-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-NEXT: vextractps $1, %xmm1, %ecx
+; X86-NEXT: vpextrd $1, %xmm0, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: divl %ecx
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: vmovd %xmm1, %edi
+; X86-NEXT: vmovd %xmm0, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: divl %edi
+; X86-NEXT: vmovd %eax, %xmm2
+; X86-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
+; X86-NEXT: vpextrd $2, %xmm1, %ecx
+; X86-NEXT: vpextrd $2, %xmm0, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: divl %ecx
+; X86-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
+; X86-NEXT: vpextrd $3, %xmm1, %ecx
+; X86-NEXT: vpextrd $3, %xmm0, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: divl %ecx
+; X86-NEXT: vpinsrd $3, %eax, %xmm2, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%esi)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_udiv_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movd %esi, %xmm2
@@ -351,6 +445,42 @@ define void @vp_udiv_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.udiv.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_srem_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_srem_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm2
+; X86-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3]
+; X86-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
+; X86-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; X86-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-NEXT: vextractps $1, %xmm1, %ecx
+; X86-NEXT: vpextrd $1, %xmm0, %eax
+; X86-NEXT: cltd
+; X86-NEXT: idivl %ecx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: vmovd %xmm1, %edi
+; X86-NEXT: vmovd %xmm0, %eax
+; X86-NEXT: cltd
+; X86-NEXT: idivl %edi
+; X86-NEXT: vmovd %edx, %xmm2
+; X86-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
+; X86-NEXT: vpextrd $2, %xmm1, %ecx
+; X86-NEXT: vpextrd $2, %xmm0, %eax
+; X86-NEXT: cltd
+; X86-NEXT: idivl %ecx
+; X86-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
+; X86-NEXT: vpextrd $3, %xmm1, %ecx
+; X86-NEXT: vpextrd $3, %xmm0, %eax
+; X86-NEXT: cltd
+; X86-NEXT: idivl %ecx
+; X86-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%esi)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_srem_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movd %esi, %xmm2
@@ -494,6 +624,42 @@ define void @vp_srem_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.srem.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_urem_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_urem_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm2
+; X86-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3]
+; X86-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
+; X86-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; X86-NEXT: vblendvps %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-NEXT: vextractps $1, %xmm1, %ecx
+; X86-NEXT: vpextrd $1, %xmm0, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: divl %ecx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: vmovd %xmm1, %edi
+; X86-NEXT: vmovd %xmm0, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: divl %edi
+; X86-NEXT: vmovd %edx, %xmm2
+; X86-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2
+; X86-NEXT: vpextrd $2, %xmm1, %ecx
+; X86-NEXT: vpextrd $2, %xmm0, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: divl %ecx
+; X86-NEXT: vpinsrd $2, %edx, %xmm2, %xmm2
+; X86-NEXT: vpextrd $3, %xmm1, %ecx
+; X86-NEXT: vpextrd $3, %xmm0, %eax
+; X86-NEXT: xorl %edx, %edx
+; X86-NEXT: divl %ecx
+; X86-NEXT: vpinsrd $3, %edx, %xmm2, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%esi)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_urem_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movd %esi, %xmm2
@@ -637,6 +803,24 @@ define void @vp_urem_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.urem.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_ashr_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_ashr_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: vpsrad %xmm2, %xmm0, %xmm2
+; X86-NEXT: vpsrlq $32, %xmm1, %xmm3
+; X86-NEXT: vpsrad %xmm3, %xmm0, %xmm3
+; X86-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
+; X86-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; X86-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; X86-NEXT: vpsrad %xmm3, %xmm0, %xmm3
+; X86-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
+; X86-NEXT: vpsrad %xmm1, %xmm0, %xmm0
+; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
+; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_ashr_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
@@ -692,6 +876,24 @@ define void @vp_ashr_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_lshr_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_lshr_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: vpsrld %xmm2, %xmm0, %xmm2
+; X86-NEXT: vpsrlq $32, %xmm1, %xmm3
+; X86-NEXT: vpsrld %xmm3, %xmm0, %xmm3
+; X86-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
+; X86-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; X86-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; X86-NEXT: vpsrld %xmm3, %xmm0, %xmm3
+; X86-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
+; X86-NEXT: vpsrld %xmm1, %xmm0, %xmm0
+; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
+; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_lshr_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
@@ -747,6 +949,16 @@ define void @vp_lshr_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_shl_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_shl_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpslld $23, %xmm1, %xmm1
+; X86-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; X86-NEXT: vcvttps2dq %xmm1, %xmm1
+; X86-NEXT: vpmulld %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_shl_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: pslld $23, %xmm1
@@ -789,6 +1001,13 @@ define void @vp_shl_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounw
declare <4 x i32> @llvm.vp.shl.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_or_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_or_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vorps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_or_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: orps %xmm1, %xmm0
@@ -807,6 +1026,13 @@ define void @vp_or_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwi
declare <4 x i32> @llvm.vp.or.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_and_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_and_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vorps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_and_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: orps %xmm1, %xmm0
@@ -825,6 +1051,13 @@ define void @vp_and_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounw
declare <4 x i32> @llvm.vp.and.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_xor_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_xor_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vxorps %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovaps %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_xor_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm1, %xmm0
@@ -843,6 +1076,13 @@ define void @vp_xor_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounw
declare <4 x i32> @llvm.vp.xor.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_abs_v4i32(<4 x i32> %a0, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_abs_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpabsd %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_abs_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm1
@@ -864,6 +1104,13 @@ define void @vp_abs_v4i32(<4 x i32> %a0, ptr %out, i32 %vp) nounwind {
declare <4 x i32> @llvm.vp.abs.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32)
define void @vp_smax_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_smax_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_smax_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm2
@@ -886,6 +1133,13 @@ define void @vp_smax_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.smax.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_smin_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_smin_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpminsd %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_smin_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm1, %xmm2
@@ -908,6 +1162,13 @@ define void @vp_smin_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.smin.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_umax_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_umax_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_umax_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
@@ -933,6 +1194,13 @@ define void @vp_umax_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) noun
declare <4 x i32> @llvm.vp.umax.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
define void @vp_umin_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %out, i32 %vp) nounwind {
+; X86-LABEL: vp_umin_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; X86-NEXT: vmovdqa %xmm0, (%eax)
+; X86-NEXT: retl
+;
; SSE-LABEL: vp_umin_v4i32:
; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
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