[llvm] [X86] Support EGPR (R16-R31) for APX (PR #67702)

[Shengchen Kan via llvm-commits]

================
@@ -158,6 +158,10 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
     case X86::GR16RegClassID:
     case X86::GR32RegClassID:
     case X86::GR64RegClassID:
+    case X86::GR8_NOREX2RegClassID:
+    case X86::GR16_NOREX2RegClassID:
+    case X86::GR32_NOREX2RegClassID:
+    case X86::GR64_NOREX2RegClassID:
----------------
KanRobert wrote:

What's the risk?
```
    Register Reg = MRI->createVirtualRegister(
        TII->getRegClass(TII->get(DstOpcode), 0, MRI->getTargetRegisterInfo(),
                         *MBB->getParent()));
    MachineInstrBuilder Bld = BuildMI(*MBB, MI, DL, TII->get(DstOpcode), Reg);
```
The code calls `getRegClass` to get the register class and then build the machine instruction with the same opcode. It looks safe to me.

In X86,   (If I remember correctly) pseudo instruction `COPY` is either a `MOV` or `KMOV`. Both of them can encode r16-31.

https://github.com/llvm/llvm-project/pull/67702