[llvm] 0b0ed8f - [RISCV] Add missing hunk to #67889 to fix test failures

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2023-10-01T11:34:57+01:00
New Revision: 0b0ed8f76a264c3677b8254d8d334de43600568f

URL: https://github.com/llvm/llvm-project/commit/0b0ed8f76a264c3677b8254d8d334de43600568f
DIFF: https://github.com/llvm/llvm-project/commit/0b0ed8f76a264c3677b8254d8d334de43600568f.diff

LOG: [RISCV] Add missing hunk to #67889 to fix test failures

Without this, various CodeGen tests fail because a
RISCV::FCVT_D_W[_IN32X] machine node is created without the rounding
mode operand.

The relevant PR was committed as bf94ba39b65d1212ea84d5783b393280e1ce7478

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 70b9041852f91f8..e90b8d49a09684a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -911,7 +911,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       break;
     }
 
-    SDNode *Res = CurDAG->getMachineNode(Opc, DL, VT, Imm);
+    SDNode *Res;
+    if (Opc == RISCV::FCVT_D_W_IN32X || Opc == RISCV::FCVT_D_W)
+      Res = CurDAG->getMachineNode(
+          Opc, DL, VT, Imm,
+          CurDAG->getTargetConstant(RISCVFPRndMode::RNE, DL, XLenVT));
+    else
+      Res = CurDAG->getMachineNode(Opc, DL, VT, Imm);
 
     // For f64 -0.0, we need to insert a fneg.d idiom.
     if (NegZeroF64)