[llvm] [X86] Support EGPR (R16-R31) for APX (PR #67702)

[Shengchen Kan via llvm-commits]

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@@ -390,42 +513,52 @@ def SSP : X86Reg<"ssp", 0>;
 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
 // cannot be encoded.
-def GR8 : RegisterClass<"X86", [i8],  8,
+def GR8 : RegisterClass<"X86", [i8], 8,
                         (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
-                             R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> {
+                         R8B, R9B, R10B, R11B, R16B, R17B, R18B, R19B, R20B,
+                         R21B, R22B, R23B, R24B, R25B, R26B, R27B, R28B, R29B,
+                         R30B, R31B, R14B, R15B, R12B, R13B)> {
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KanRobert wrote:

b/c R12-R15 are callee-saved registers. It's explained at line 86.

As for the order of R12-R15 itself， I just keep the old behavior. 

https://github.com/llvm/llvm-project/pull/67702