[llvm] [X86] Support EGPR (R16-R31) for APX (PR #67702)
    Shengchen Kan via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Sat Sep 30 20:32:35 PDT 2023
    
    
  
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@@ -491,6 +624,27 @@ def GR32_NOREX : RegisterClass<"X86", [i32], 32,
 // GR64_NOREX - GR64 registers which do not require a REX prefix.
 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
                             (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
+// GeneratePressureSet = 0 here is a temporary workaround for lots of
+// LIT fail for xisa. Whether enabling in the future still needs discussion.
+let GeneratePressureSet = 0 in {
+// GR8_NOREX2 - GR8 registers which do not require a REX2 prefix.
----------------
KanRobert wrote:
`NOREX2` can not encode R16-R31, which is subtracted.
` (sub GR8,  (sequence "R%uB", 16, 31))`
https://github.com/llvm/llvm-project/pull/67702
    
    
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