[PATCH] D156444: [llvm][RISCV][IR] Zext flag in IR for RISC-V

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Bitcode/Reader/BitcodeReader.cpp:4874
       if (OpNum < Record.size()) {
-        if (Opc == Instruction::Add ||
-            Opc == Instruction::Sub ||
-            Opc == Instruction::Mul ||
-            Opc == Instruction::Shl) {
-          if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP))
-            cast<BinaryOperator>(I)->setHasNoSignedWrap(true);
+        if (Opc == Instruction::Add || Opc == Instruction::Sub ||
+            Opc == Instruction::Mul || Opc == Instruction::Shl) {
----------------
karouzakisp wrote:
> craig.topper wrote:
> > Is this reformatting existing code that you aren't changing?
> Probably 
> git clang-format
> reformatted it. 
> Should I reformat it back?
This should be reformatted back the way it was.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156444/new/

https://reviews.llvm.org/D156444