[llvm] Add SVML calling convention (PR #67884)
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Sat Sep 30 06:56:32 PDT 2023
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git-clang-format --diff dc1dc60ea8786d4a2462d157842501d76593f9e7 e40e69dc1b8a78bc85cf7c1892e45b57d237d552 -- llvm/include/llvm/AsmParser/LLToken.h llvm/include/llvm/IR/CallingConv.h llvm/lib/AsmParser/LLLexer.cpp llvm/lib/AsmParser/LLParser.cpp llvm/lib/IR/AsmWriter.cpp llvm/lib/IR/Verifier.cpp llvm/lib/Target/X86/X86ISelLoweringCall.cpp llvm/lib/Target/X86/X86RegisterInfo.cpp llvm/lib/Target/X86/X86Subtarget.h
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diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp
index 9dec60090..490711318 100644
--- a/llvm/lib/AsmParser/LLParser.cpp
+++ b/llvm/lib/AsmParser/LLParser.cpp
@@ -2037,9 +2037,15 @@ bool LLParser::parseOptionalCallingConv(unsigned &CC) {
case lltok::kw_spir_kernel: CC = CallingConv::SPIR_KERNEL; break;
case lltok::kw_spir_func: CC = CallingConv::SPIR_FUNC; break;
case lltok::kw_intel_ocl_bicc: CC = CallingConv::Intel_OCL_BI; break;
- case lltok::kw_intel_svmlcc128:CC = CallingConv::Intel_SVML128; break;
- case lltok::kw_intel_svmlcc256:CC = CallingConv::Intel_SVML256; break;
- case lltok::kw_intel_svmlcc512:CC = CallingConv::Intel_SVML512; break;
+ case lltok::kw_intel_svmlcc128:
+ CC = CallingConv::Intel_SVML128;
+ break;
+ case lltok::kw_intel_svmlcc256:
+ CC = CallingConv::Intel_SVML256;
+ break;
+ case lltok::kw_intel_svmlcc512:
+ CC = CallingConv::Intel_SVML512;
+ break;
case lltok::kw_x86_64_sysvcc: CC = CallingConv::X86_64_SysV; break;
case lltok::kw_win64cc: CC = CallingConv::Win64; break;
case lltok::kw_webkit_jscc: CC = CallingConv::WebKit_JS; break;
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index 768098685..b69c602ac 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -304,9 +304,15 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
case CallingConv::X86_RegCall: Out << "x86_regcallcc"; break;
case CallingConv::X86_VectorCall:Out << "x86_vectorcallcc"; break;
case CallingConv::Intel_OCL_BI: Out << "intel_ocl_bicc"; break;
- case CallingConv::Intel_SVML128: Out << "intel_svmlcc128"; break;
- case CallingConv::Intel_SVML256: Out << "intel_svmlcc256"; break;
- case CallingConv::Intel_SVML512: Out << "intel_svmlcc512"; break;
+ case CallingConv::Intel_SVML128:
+ Out << "intel_svmlcc128";
+ break;
+ case CallingConv::Intel_SVML256:
+ Out << "intel_svmlcc256";
+ break;
+ case CallingConv::Intel_SVML512:
+ Out << "intel_svmlcc512";
+ break;
case CallingConv::ARM_APCS: Out << "arm_apcscc"; break;
case CallingConv::ARM_AAPCS: Out << "arm_aapcscc"; break;
case CallingConv::ARM_AAPCS_VFP: Out << "arm_aapcs_vfpcc"; break;
diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
index 06b0f182e..2a28acc4e 100644
--- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
+++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp
@@ -1648,7 +1648,7 @@ void VarArgsLoweringHelper::forwardMustTailParameters(SDValue &Chain) {
// FIXME: Only some x86_32 calling conventions support AVX512.
if (Subtarget.useAVX512Regs() &&
(is64Bit() || (CallConv == CallingConv::X86_VectorCall ||
- CallConv == CallingConv::Intel_OCL_BI ||
+ CallConv == CallingConv::Intel_OCL_BI ||
CallConv == CallingConv::Intel_SVML512)))
VecVT = MVT::v16f32;
else if (Subtarget.hasAVX())
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 1f5920593..32450993a 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -274,27 +274,33 @@ X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
}
}
-static std::pair<const uint32_t *, const MCPhysReg *> getSVMLRegMaskAndSaveList(
- bool Is64Bit, bool IsWin64, CallingConv::ID CC) {
+static std::pair<const uint32_t *, const MCPhysReg *>
+getSVMLRegMaskAndSaveList(bool Is64Bit, bool IsWin64, CallingConv::ID CC) {
assert(CC >= CallingConv::Intel_SVML128 && CC <= CallingConv::Intel_SVML512);
- unsigned Abi = CC - CallingConv::Intel_SVML128 ; // 0 - 128, 1 - 256, 2 - 512
+ unsigned Abi = CC - CallingConv::Intel_SVML128; // 0 - 128, 1 - 256, 2 - 512
const std::pair<const uint32_t *, const MCPhysReg *> Abi64[] = {
- std::make_pair(CSR_64_Intel_SVML_RegMask, CSR_64_Intel_SVML_SaveList),
- std::make_pair(CSR_64_Intel_SVML_AVX_RegMask, CSR_64_Intel_SVML_AVX_SaveList),
- std::make_pair(CSR_64_Intel_SVML_AVX512_RegMask, CSR_64_Intel_SVML_AVX512_SaveList),
+ std::make_pair(CSR_64_Intel_SVML_RegMask, CSR_64_Intel_SVML_SaveList),
+ std::make_pair(CSR_64_Intel_SVML_AVX_RegMask,
+ CSR_64_Intel_SVML_AVX_SaveList),
+ std::make_pair(CSR_64_Intel_SVML_AVX512_RegMask,
+ CSR_64_Intel_SVML_AVX512_SaveList),
};
const std::pair<const uint32_t *, const MCPhysReg *> AbiWin64[] = {
- std::make_pair(CSR_Win64_Intel_SVML_RegMask, CSR_Win64_Intel_SVML_SaveList),
- std::make_pair(CSR_Win64_Intel_SVML_AVX_RegMask, CSR_Win64_Intel_SVML_AVX_SaveList),
- std::make_pair(CSR_Win64_Intel_SVML_AVX512_RegMask, CSR_Win64_Intel_SVML_AVX512_SaveList),
+ std::make_pair(CSR_Win64_Intel_SVML_RegMask,
+ CSR_Win64_Intel_SVML_SaveList),
+ std::make_pair(CSR_Win64_Intel_SVML_AVX_RegMask,
+ CSR_Win64_Intel_SVML_AVX_SaveList),
+ std::make_pair(CSR_Win64_Intel_SVML_AVX512_RegMask,
+ CSR_Win64_Intel_SVML_AVX512_SaveList),
};
const std::pair<const uint32_t *, const MCPhysReg *> Abi32[] = {
- std::make_pair(CSR_32_Intel_SVML_RegMask, CSR_32_Intel_SVML_SaveList),
- std::make_pair(CSR_32_Intel_SVML_RegMask, CSR_32_Intel_SVML_SaveList),
- std::make_pair(CSR_32_Intel_SVML_AVX512_RegMask, CSR_32_Intel_SVML_AVX512_SaveList),
+ std::make_pair(CSR_32_Intel_SVML_RegMask, CSR_32_Intel_SVML_SaveList),
+ std::make_pair(CSR_32_Intel_SVML_RegMask, CSR_32_Intel_SVML_SaveList),
+ std::make_pair(CSR_32_Intel_SVML_AVX512_RegMask,
+ CSR_32_Intel_SVML_AVX512_SaveList),
};
if (Is64Bit) {
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https://github.com/llvm/llvm-project/pull/67884
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