[llvm] [AMDGPU][IGLP] SingleWaveOpt: Cache DSW Counters from PreRA + Don't collect PERMs for generic VALU SG (PR #67759)

[Jeffrey Byrnes via llvm-commits]

jrbyrnes wrote:

Latest commit adds "caching" of the DSW counters from PreRA scheduling. While this avoids recalculation in the postRA pass, that isn't the main purpose.

This is required because of physical register dependencies in PostRA scheduling -- they alter the DAG s.t. our counters may become incorrect -- which alters the layout of the pipeline. By preserving the values from PreRA, we can be sure that we accurately construct the pipeline.

Tighter matching on VALU / Perm essentially provided a workaround to cope with this transient behavior. That said, the further constraint on SG matching should only make the mutation more robust.

https://github.com/llvm/llvm-project/pull/67759