[llvm] cc9ba56 - [test] -march -> -mtriple (#67741)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 29 10:43:28 PDT 2023
Author: Visoiu Mistrih Francis
Date: 2023-09-29T10:43:23-07:00
New Revision: cc9ba5600e540fd4e059d20591917962a6df043d
URL: https://github.com/llvm/llvm-project/commit/cc9ba5600e540fd4e059d20591917962a6df043d
DIFF: https://github.com/llvm/llvm-project/commit/cc9ba5600e540fd4e059d20591917962a6df043d.diff
LOG: [test] -march -> -mtriple (#67741)
Similar to 806761a
Added:
Modified:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
llvm/test/CodeGen/RISCV/copy-frameindex.mir
llvm/test/CodeGen/RISCV/live-sp.mir
llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
llvm/test/CodeGen/RISCV/machine-outliner-position.mir
llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir
llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
llvm/test/CodeGen/RISCV/machineoutliner.mir
llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
llvm/test/CodeGen/RISCV/stack-inst-compress.mir
llvm/test/CodeGen/RISCV/stack-slot-coloring.mir
llvm/test/CodeGen/RISCV/verify-instr.mir
llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir
llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir
llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
index c063e5a97c394ec..2ef5de501ee7116 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
index 84cc55f422a6a0c..1c3e92d6669d6d1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
index d02b0b6f0e0124d..868bc2c37778e5e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
index 9b37c12bf3a3599..f748f0811a99c67 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir
index 123596b2cef3583..a0ec98b145470ea 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir
index 1251a812bba09cf..bb15aa50bb561f7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir
index bc36cbfced584ef..459511eb94358cf 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir
index 3f960985b617e14..8512af316f54108 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
---
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
index 5e17407f9bfb9a0..6f8d76953de4fb7 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -mattr=+m -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
index 6d87e3dcb4c36c2..26120f770413623 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+m -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
index eac5201e4fe2537..7e02e7d25d2da9e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
index 0141dbaa2edc8a0..c162ac0b6e996c3 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
index 0ea1b3162e9aa0e..e6a8f4100f4e769 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
index 965388a0f355bac..8cea5fd19007c9c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
index 86b5fc64abd33e8..36146c158d8a591 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
index 4f0d973808b6e37..ed86fb2725c7a01 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
index a1d76ec3d73fb80..64533de67d3b695 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
index 80e73f93e80e6bc..b8bedfae987d31b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
index b0f86991f275668..e7db66b37bd2bfd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
index e08cebdcba2e76a..fe5c799187480d4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
index 93999fd93c8342c..df3f6319debfa5c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
index 6dc46fca6f256d0..903cc868e69e4e5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
index 1f70ecf442d0b85..3ea9a51dc4203f1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s
diff --git a/llvm/test/CodeGen/RISCV/copy-frameindex.mir b/llvm/test/CodeGen/RISCV/copy-frameindex.mir
index 87636e0a96b40a7..f220751daad4c84 100644
--- a/llvm/test/CodeGen/RISCV/copy-frameindex.mir
+++ b/llvm/test/CodeGen/RISCV/copy-frameindex.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s
--- |
define void @sink_addi_fi(i32 %0) !dbg !5 {
diff --git a/llvm/test/CodeGen/RISCV/live-sp.mir b/llvm/test/CodeGen/RISCV/live-sp.mir
index 2210fd1a8a927ec..5df6a79755cb460 100644
--- a/llvm/test/CodeGen/RISCV/live-sp.mir
+++ b/llvm/test/CodeGen/RISCV/live-sp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=prologepilog -simplify-mir -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -simplify-mir -o - %s | FileCheck %s
# verify live-on-entry registers are not marked killed by spills
--- |
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir b/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
index fa0ef9e76f3c7f7..6ecca6a1b18ef89 100644
--- a/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir
@@ -1,6 +1,6 @@
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s
# CFIs are invisible (they can be outlined, but won't actually impact the outlining result) if there
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-position.mir b/llvm/test/CodeGen/RISCV/machine-outliner-position.mir
index e6c101758a937f0..715e212eecabb39 100644
--- a/llvm/test/CodeGen/RISCV/machine-outliner-position.mir
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-position.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=RV64I-MO %s
# Position instructions are illegal to outline. The first instruction won't be outlined
diff --git a/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir b/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir
index 885db0aa5023cdb..563d155fd5dc3ff 100644
--- a/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir
+++ b/llvm/test/CodeGen/RISCV/machineoutliner-jumptable.mir
@@ -1,6 +1,6 @@
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=RV64I-MO %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir b/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
index 91bc20e15da78fa..34f7a93b6a168c3 100644
--- a/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
+++ b/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck %s
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=CHECK-FS %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir --function-sections -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=CHECK-FS %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/machineoutliner.mir b/llvm/test/CodeGen/RISCV/machineoutliner.mir
index 3a2d5062872538a..0221257354fcfa0 100644
--- a/llvm/test/CodeGen/RISCV/machineoutliner.mir
+++ b/llvm/test/CodeGen/RISCV/machineoutliner.mir
@@ -1,6 +1,6 @@
-# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=CHECK,RV32I-MO %s
-# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=CHECK,RV64I-MO %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
index fcd78ee757eaa11..de941b8739a816b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
--- |
define void @add_scalable_offset(
diff --git a/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir b/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
index 20b3a5297d723a6..554cf17eb79c52c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+v -run-pass=register-coalescer %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer %s -o - 2>&1 | FileCheck %s
# This test used to crash in the register coalescer when the target would
# return the out-of-bounds CommuteAnyOperandIndex for one of its commutable
diff --git a/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir b/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
index ab9483c8616ff97..3b41e92f437309f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+v -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+v -o - %s \
# RUN: -stop-after=prologepilog | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
index e58c975e512ee1f..f6d9feea47b5a5f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+v -verify-machineinstrs \
+# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
# RUN: -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
index ff317234c468c78..2971b9ee59e74ec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
--- |
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
diff --git a/llvm/test/CodeGen/RISCV/stack-inst-compress.mir b/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
index 5dcf1e9f8cbbf20..6721ff11d99b7bb 100644
--- a/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
+++ b/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-# RUN: llc -march=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=CHECK-RV32-NO-COM %s
-# RUN: llc -march=riscv32 -mattr=+c -x mir -run-pass=prologepilog \
+# RUN: llc -mtriple=riscv32 -mattr=+c -x mir -run-pass=prologepilog \
# RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-RV32-COM %s
-# RUN: llc -march=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=CHECK-RV64-NO-COM %s
-# RUN: llc -march=riscv64 -mattr=+c -x mir -run-pass=prologepilog \
+# RUN: llc -mtriple=riscv64 -mattr=+c -x mir -run-pass=prologepilog \
# RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-RV64-COM %s
--- |
define dso_local void @_Z15stack_size_2048v() {
diff --git a/llvm/test/CodeGen/RISCV/stack-slot-coloring.mir b/llvm/test/CodeGen/RISCV/stack-slot-coloring.mir
index 1fb2b7685bafb1a..17bbcc2981bb8a0 100644
--- a/llvm/test/CodeGen/RISCV/stack-slot-coloring.mir
+++ b/llvm/test/CodeGen/RISCV/stack-slot-coloring.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv32 -run-pass=greedy,virtregrewriter,stack-slot-coloring %s -o - 2>&1 | FileCheck %s
--- |
define dso_local i32 @main() local_unnamed_addr {
diff --git a/llvm/test/CodeGen/RISCV/verify-instr.mir b/llvm/test/CodeGen/RISCV/verify-instr.mir
index 58fcbc3e47de2e7..622163659a9dd73 100644
--- a/llvm/test/CodeGen/RISCV/verify-instr.mir
+++ b/llvm/test/CodeGen/RISCV/verify-instr.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
# CHECK: *** Bad machine code: Invalid immediate ***
# CHECK: - instruction: $x2 = ADDI $x1, 10000
diff --git a/llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir b/llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir
index 2ec62ae096f4f68..68593caafc797b7 100644
--- a/llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir
+++ b/llvm/test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -mtriple=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
# REQUIRES: riscv-registered-target
# This test checks that the G_BRINDIRECT is an indirect branch by leveraging
diff --git a/llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir b/llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir
index 9a5df6e00c3381c..e5c4d41e1412b53 100644
--- a/llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir
+++ b/llvm/test/MachineVerifier/test_g_brjt_is_indirect_branch.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -mtriple=riscv32 -o - -run-pass=none -verify-machineinstrs %s | FileCheck %s
# REQUIRES: riscv-registered-target
# This test checks that the G_BRJT is an indirect branch by leveraging RISCV's
diff --git a/llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll b/llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
index 06bd4babad710c0..9c896796760ff60 100644
--- a/llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
+++ b/llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -march=riscv32 -mattr=+zve32x,+zvl32b -interleaved-access -S | FileCheck %s -check-prefix=ZVL32B
+; RUN: opt < %s -mtriple=riscv32 -mattr=+zve32x,+zvl32b -interleaved-access -S | FileCheck %s -check-prefix=ZVL32B
; RUN: opt < %s -mtriple=riscv32 -mattr=+zve32x,+zvl128b -interleaved-access -S | FileCheck %s -check-prefix=ZVL128B
; Make sure that we don't lower interleaved loads that won't fit into the minimum vlen
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