[PATCH] D155472: [DAG] Attempt shl narrowing in SimplifyDemandedBits

Fri Sep 29 08:24:15 PDT 2023

goldstein.w.n added a comment.

Can the changes to `X86ISelDAGToDAG.cpp` and `X86ISelLowering.cpp` that are there to handle the regressions be split to a prior patch?
They look properly standalone.

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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1799
+          if (IsNUW || DemandedBits.countLeadingZeros() >= HalfWidth) {
+            SDValue NewOp = TLO.DAG.getNode(ISD::TRUNCATE, dl, HalfVT, Op0);
+            SDValue NewShiftAmt = TLO.DAG.getShiftAmountConstant(
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Nit: Took me a bit to find this. Would think it would be more natural to put just ahead of `NewShift` (where it's used).

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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1803
+            unsigned NumSignBits = TLO.DAG.ComputeNumSignBits(Op0, Depth + 1);
+            bool IsNSW = NumSignBits > (ShAmt + HalfWidth);
+            SDNodeFlags Flags;
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Hmm, so with the optimization to do the knownbits methods by hand, the code is definetly harder to follow. Can you add a few comments explaining the checks taking place?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155472/new/

https://reviews.llvm.org/D155472