[llvm] 2a0ec5f - [AMDGPU] Add GFX11.5 s_singleuse_vdst instruction (#67536)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 29 07:05:17 PDT 2023
Author: Jay Foad
Date: 2023-09-29T15:05:13+01:00
New Revision: 2a0ec5f1acfad2d407c1c8076f03a83094ca30dd
URL: https://github.com/llvm/llvm-project/commit/2a0ec5f1acfad2d407c1c8076f03a83094ca30dd
DIFF: https://github.com/llvm/llvm-project/commit/2a0ec5f1acfad2d407c1c8076f03a83094ca30dd.diff
LOG: [AMDGPU] Add GFX11.5 s_singleuse_vdst instruction (#67536)
Added:
llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/GCNSubtarget.h
llvm/lib/Target/AMDGPU/SOPInstructions.td
llvm/test/MC/AMDGPU/gfx11_unsupported.s
llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 924144c5366f37e..bf5a7b0a96977c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -797,6 +797,12 @@ def FeatureSALUFloatInsts : SubtargetFeature<"salu-float",
"Has SALU floating point instructions"
>;
+def FeatureVGPRSingleUseHintInsts : SubtargetFeature<"vgpr-singleuse-hint",
+ "HasVGPRSingleUseHintInsts",
+ "true",
+ "Has single-use VGPR hint instructions"
+>;
+
//===------------------------------------------------------------===//
// Subtarget Features (options and debugging)
//===------------------------------------------------------------===//
@@ -1390,12 +1396,14 @@ def FeatureISAVersion11_0_3 : FeatureSet<
def FeatureISAVersion11_5_0 : FeatureSet<
!listconcat(FeatureISAVersion11_Common.Features,
[FeatureSALUFloatInsts,
- FeatureDPPSrc1SGPR])>;
+ FeatureDPPSrc1SGPR,
+ FeatureVGPRSingleUseHintInsts])>;
def FeatureISAVersion11_5_1 : FeatureSet<
!listconcat(FeatureISAVersion11_Common.Features,
[FeatureSALUFloatInsts,
FeatureDPPSrc1SGPR,
+ FeatureVGPRSingleUseHintInsts,
FeatureGFX11FullVGPRs])>;
//===----------------------------------------------------------------------===//
@@ -1909,6 +1917,9 @@ def HasNotMADIntraFwdBug : Predicate<"!Subtarget->hasMADIntraFwdBug()">;
def HasSALUFloatInsts : Predicate<"Subtarget->hasSALUFloatInsts()">,
AssemblerPredicate<(all_of FeatureSALUFloatInsts)>;
+def HasVGPRSingleUseHintInsts : Predicate<"Subtarget->hasVGPRSingleUseHintInsts()">,
+ AssemblerPredicate<(all_of FeatureVGPRSingleUseHintInsts)>;
+
def HasGDS : Predicate<"Subtarget->hasGDS()">;
def HasGWS : Predicate<"Subtarget->hasGWS()">;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index e7d46c0df434601..ce538f086cc368e 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -194,6 +194,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasPackedTID = false;
bool ScalarizeGlobal = false;
bool HasSALUFloatInsts = false;
+ bool HasVGPRSingleUseHintInsts = false;
bool HasVcmpxPermlaneHazard = false;
bool HasVMEMtoScalarWriteHazard = false;
@@ -1145,6 +1146,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasSALUFloatInsts() const { return HasSALUFloatInsts; }
+ bool hasVGPRSingleUseHintInsts() const { return HasVGPRSingleUseHintInsts; }
+
/// Return the maximum number of waves per SIMD for kernels using \p SGPRs
/// SGPRs
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 90b89e9ed4055ae..f3309049e7a7fd9 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1558,6 +1558,11 @@ let SubtargetPredicate = isGFX11Plus in {
"$simm16">;
} // End SubtargetPredicate = isGFX11Plus
+let SubtargetPredicate = HasVGPRSingleUseHintInsts in {
+ def S_SINGLEUSE_VDST :
+ SOPP_Pseudo<"s_singleuse_vdst", (ins s16imm:$simm16), "$simm16">;
+} // End SubtargetPredicate = HasVGPRSingeUseHintInsts
+
//===----------------------------------------------------------------------===//
// SOP1 Patterns
//===----------------------------------------------------------------------===//
@@ -2267,6 +2272,12 @@ defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx11<0x03b>;
defm S_ICACHE_INV : SOPP_Real_32_gfx11<0x03c>;
defm S_BARRIER : SOPP_Real_32_gfx11<0x03d>;
+//===----------------------------------------------------------------------===//
+// SOPP - GFX1150
+//===----------------------------------------------------------------------===//
+
+defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11<0x013>;
+
//===----------------------------------------------------------------------===//
// SOPP - GFX6, GFX7, GFX8, GFX9, GFX10
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
new file mode 100644
index 000000000000000..463e9cade7f9c0c
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
@@ -0,0 +1,10 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1150 -show-encoding %s | FileCheck --check-prefixes=GFX1150 %s
+
+s_singleuse_vdst 0x0000
+// GFX1150: encoding: [0x00,0x00,0x93,0xbf]
+
+s_singleuse_vdst 0xffff
+// GFX1150: encoding: [0xff,0xff,0x93,0xbf]
+
+s_singleuse_vdst 0x1234
+// GFX1150: encoding: [0x34,0x12,0x93,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx11_unsupported.s b/llvm/test/MC/AMDGPU/gfx11_unsupported.s
index 5e9714be224edcf..3b1b7e47b2143cb 100644
--- a/llvm/test/MC/AMDGPU/gfx11_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx11_unsupported.s
@@ -1980,3 +1980,6 @@ s_cmp_neq_f16 s1, s2
s_cmp_nlt_f16 s1, s2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+s_singleuse_vdst 0x1234
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
index 8da7e5ac2d88b38..bf2c55ef2e77b2b 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
@@ -5,6 +5,10 @@
# GCN: warning: invalid instruction encoding
0xdf,0x00,0x00,0x02
+# this is s_singleuse_vdst 0x1234, which is only valid on gfx1150
+# GFX11: warning: invalid instruction encoding
+0x34,0x12,0x93,0xbf
+
# this is buffer_atomic_csub_u32 v5, off, s[8:11], s3 offset:4095. Invalid without glc
# GFX11: warning: invalid instruction encoding
0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x03
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
new file mode 100644
index 000000000000000..ddeb70a55969796
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1150 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1150 %s
+
+# GFX1150: s_singleuse_vdst 0x0 ; encoding: [0x00,0x00,0x93,0xbf]
+0x00,0x00,0x93,0xbf
+
+# GFX1150: s_singleuse_vdst 0xffff ; encoding: [0xff,0xff,0x93,0xbf]
+0xff,0xff,0x93,0xbf
+
+# GFX1150: s_singleuse_vdst 0x1234 ; encoding: [0x34,0x12,0x93,0xbf]
+0x34,0x12,0x93,0xbf
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