[llvm] [AMDGPU] Use absolute relocations when compiling for AMDPAL (PR #67791)

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``````````bash
git-clang-format --diff 6dd96d6e80e9b3679a6161c590c60e0e99549b89 13e1acae7e24bf6519e8eb3b940c9c58d090b9a4 -- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index f04f85b7deaa..993f50f15247 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2768,48 +2768,47 @@ bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(Register DstReg, LLT PtrTy,
   return true;
  }
 
- 
  // Emit a ABS32_LO / ABS32_HI relocation stub.
  void AMDGPULegalizerInfo::buildAbsGlobalAddress(
-   Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
+     Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
      int64_t Offset, MachineRegisterInfo &MRI) const {
-  bool IsDwordTy = PtrTy.getSizeInBits() == 32;
+   bool IsDwordTy = PtrTy.getSizeInBits() == 32;
 
-  LLT S32 = LLT::scalar(32);
+   LLT S32 = LLT::scalar(32);
 
-  Register AddrDst;
-  if (IsDwordTy) {
-    AddrDst = MRI.createGenericVirtualRegister(S32);
-    MRI.setRegClass(AddrDst, &AMDGPU::SReg_32RegClass);
-  } else {
-    assert(PtrTy.getSizeInBits() == 64 &&
-           "Must provide a 64-bit pointer type!");
-    AddrDst = MRI.createGenericVirtualRegister(LLT::scalar(64));
-    MRI.setRegClass(AddrDst, &AMDGPU::SReg_64RegClass);
-  }
+   Register AddrDst;
+   if (IsDwordTy) {
+     AddrDst = MRI.createGenericVirtualRegister(S32);
+     MRI.setRegClass(AddrDst, &AMDGPU::SReg_32RegClass);
+   } else {
+     assert(PtrTy.getSizeInBits() == 64 &&
+            "Must provide a 64-bit pointer type!");
+     AddrDst = MRI.createGenericVirtualRegister(LLT::scalar(64));
+     MRI.setRegClass(AddrDst, &AMDGPU::SReg_64RegClass);
+   }
 
-  SmallVector<Register> Operands;
+   SmallVector<Register> Operands;
 
-  Register AddrLo = MRI.createGenericVirtualRegister(S32);
-  MRI.setRegClass(AddrLo, &AMDGPU::SReg_32RegClass);
+   Register AddrLo = MRI.createGenericVirtualRegister(S32);
+   MRI.setRegClass(AddrLo, &AMDGPU::SReg_32RegClass);
 
-  B.buildInstr(AMDGPU::S_MOV_B32)
-      .addDef(AddrLo)
-      .addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_LO);
+   B.buildInstr(AMDGPU::S_MOV_B32)
+       .addDef(AddrLo)
+       .addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_LO);
 
-  Operands.push_back(AddrLo);
+   Operands.push_back(AddrLo);
 
-  if (!IsDwordTy) {
-    Register AddrHi = MRI.createGenericVirtualRegister(S32);
-    MRI.setRegClass(AddrHi, &AMDGPU::SReg_32RegClass);
-    B.buildInstr(AMDGPU::S_MOV_B32)
-        .addDef(AddrHi)
-        .addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_HI);
+   if (!IsDwordTy) {
+     Register AddrHi = MRI.createGenericVirtualRegister(S32);
+     MRI.setRegClass(AddrHi, &AMDGPU::SReg_32RegClass);
+     B.buildInstr(AMDGPU::S_MOV_B32)
+         .addDef(AddrHi)
+         .addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_HI);
 
-    Operands.push_back(AddrHi);
-  }
+     Operands.push_back(AddrHi);
+   }
 
-  B.buildMergeValues(DstReg, Operands);
+   B.buildMergeValues(DstReg, Operands);
  }
 
 bool AMDGPULegalizerInfo::legalizeGlobalValue(
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 117a803e2b49..056172eca696 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5708,7 +5708,7 @@ bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
          AMDGPU::shouldEmitConstantsToTextSection(TT);
 }
 
-bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {  
+bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
   if (Subtarget->isAmdPalOS())
     return false;
 
@@ -6743,7 +6743,7 @@ SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
 
   if (shouldEmitFixup(GV))
     return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
-  
+
   if (shouldEmitPCReloc(GV))
     return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
                                    SIInstrInfo::MO_REL32);

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https://github.com/llvm/llvm-project/pull/67791