[llvm] VectorWiden pass to widen aleady vectorized instrctions (PR #67029)

[Dinar Temirbulatov via llvm-commits]

dtemirbulatov wrote:

> > > For the example in the description, isn't the issue that the SLP vectorizer doesn't support generating code for scalable vectors? Or has this recently been implemented?
> > 
> > 
> > Scalable vectors are meaningless for SLP, it always operates with constant number of scalars/fixed vectors size (equal it number of scalars).
> 
> It's not clear from the description, but the godbolt example passes `-msve-vector-bits=256`, which IIUC allows LLVM to assume the SVE vector registers are exactly 256 bits wide, allowing SLP using that assumption. In the example, 2 128 bit NEON `add` are replaced with a single SVE `add`, which implies the code is only correct for system where the registers have at least 256 bits unless I am missing anything.

Yes, that is correct. We are targeting 256-bit register SVE hardware in the example.

https://github.com/llvm/llvm-project/pull/67029