[llvm] [RISCV] Match prefetch address with offset (PR #66072)

[Craig Topper via llvm-commits]

================
@@ -2442,6 +2448,95 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
   return true;
 }
 
+/// Similar to SelectAddrRegImm, except that the least significant 5 bits of
+/// Offset shoule be all zeros.
+bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
+                                                 SDValue &Offset) {
+  if (SelectAddrFrameIndex(Addr, Base, Offset))
+    return true;
+
+  SDLoc DL(Addr);
+  MVT VT = Addr.getSimpleValueType();
+
+  if (Addr.getOpcode() == RISCVISD::ADD_LO) {
+    Base = Addr;
+    Offset = CurDAG->getTargetConstant(0, DL, VT);
+    return true;
+  }
+
+  if (CurDAG->isBaseWithConstantOffset(Addr)) {
+    int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
+    if (isInt<12>(CVal)) {
+      Base = Addr.getOperand(0);
+      if (Base.getOpcode() == RISCVISD::ADD_LO) {
+        SDValue LoOperand = Base.getOperand(1);
+        if (auto *GA = dyn_cast<GlobalAddressSDNode>(LoOperand)) {
+          const DataLayout &DL = CurDAG->getDataLayout();
+          Align Alignment = commonAlignment(
+              GA->getGlobal()->getPointerAlignment(DL), GA->getOffset());
+          int64_t CombinedOffset = CVal + GA->getOffset();
+          if (((CombinedOffset & 0b11111) == 0) &&
----------------
topperc wrote:

CombinedOffset being aligned isn't enough. You would also need the global itself to be aligned to 32 byte aligned. If the global isn't aligned, the base address of global + CombinedOffset might not be 32 byte aligned.

https://github.com/llvm/llvm-project/pull/66072