[llvm] [RISCV][GlobalISel] Legalize G_FRAME_INDEX (PR #67746)

Nitin John Raj via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 28 14:55:36 PDT 2023


https://github.com/nitinjohnraj updated https://github.com/llvm/llvm-project/pull/67746

>From a267b29bfceac1ac9b6503e67646c534009ea415 Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin.raj at sifive.com>
Date: Tue, 26 Sep 2023 13:16:46 -0700
Subject: [PATCH 1/2] [RISCV][GlobalISel] Legalize G_FRAME_INDEX

---
 llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 1f9b80856bbe134..3a175bacc90834f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -167,6 +167,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
         .widenScalarToNextPow2(0);
   }
 
+  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
+
   getLegacyLegalizerInfo().computeTables();
 }
 

>From ac4581f3eb81c6e307c052a2fba5033ffbe6a7f7 Mon Sep 17 00:00:00 2001
From: Nitin John Raj <nitin.raj at sifive.com>
Date: Thu, 28 Sep 2023 14:55:25 -0700
Subject: [PATCH 2/2] Add tests

---
 .../legalizer/rv32/legalize-frame-index.mir   | 29 +++++++++++++++++++
 .../legalizer/rv64/legalize-frame-index.mir   | 29 +++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-frame-index.mir
 create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-frame-index.mir

diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-frame-index.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-frame-index.mir
new file mode 100644
index 000000000000000..1e1879ac21b9082
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-frame-index.mir
@@ -0,0 +1,29 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+--- |
+
+  define ptr @alloca32() {
+  entry:
+    %ptr0 = alloca i32, align 4
+    ret ptr %ptr0
+  }
+
+...
+---
+name:            alloca32
+stack:
+  - { id: 0, name: ptr0, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: alloca32
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr0
+    ; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = G_FRAME_INDEX %stack.0.ptr0
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-frame-index.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-frame-index.mir
new file mode 100644
index 000000000000000..6d083d8bde3cfce
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-frame-index.mir
@@ -0,0 +1,29 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+--- |
+
+  define ptr @alloca64() {
+  entry:
+    %ptr0 = alloca i64, align 4
+    ret ptr %ptr0
+  }
+
+...
+---
+name:            alloca64
+stack:
+  - { id: 0, name: ptr0, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: alloca64
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr0
+    ; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = G_FRAME_INDEX %stack.0.ptr0
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...



More information about the llvm-commits mailing list