[PATCH] D159140: [GlobalISel] LegalizationArtifactCombiner: Elide redundant G_AND
Tobias Stadler via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 28 12:46:21 PDT 2023
tobias-stadler updated this revision to Diff 557461.
tobias-stadler added a comment.
Add suggested comment + Rebase.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D159140/new/
https://reviews.llvm.org/D159140
Files:
llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll
llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-cse.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshl.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fshr.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptrtoint.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
llvm/test/CodeGen/AArch64/zext.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-cse-leaves-dead-cast.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-mul-ext.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-store.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-mul-ext.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-store.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
More information about the llvm-commits
mailing list