[llvm] [AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on supported subtargets (PR #67461)

[Mirko Brkušanin via llvm-commits]

mbrkusanin wrote:

- clang-format
- added disassembler test
- added assert to check if size of src0 and src1 is same for dpp that would be generated
- added '---' to .mir test
- test formatting
- rebase

https://github.com/llvm/llvm-project/pull/67461