[llvm] e0a48c0 - [InlineAsm] add comments for NumOperands and ConstraintType (#67474)

[via llvm-commits]

Author: Nick Desaulniers
Date: 2023-09-28T08:24:56-07:00
New Revision: e0a48c065b0332c6a76df6a6d5642e8e8ebb6f91

URL: https://github.com/llvm/llvm-project/commit/e0a48c065b0332c6a76df6a6d5642e8e8ebb6f91
DIFF: https://github.com/llvm/llvm-project/commit/e0a48c065b0332c6a76df6a6d5642e8e8ebb6f91.diff

LOG: [InlineAsm] add comments for NumOperands and ConstraintType (#67474)

Splitting up patches for #20571. I found these comments generally useful
to add and not predicated on those changes. Hopefully they help future
travelers.

Added: 
    

Modified: 
    llvm/include/llvm/IR/InlineAsm.h
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index 0c0389871fc2f9b..969ad42816a7e52 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -277,14 +277,19 @@ class InlineAsm final : public Value {
   // on INLINEASM and INLINEASM_BR MachineInstr's.
   //
   // The encoding of Flag is currently:
-  //   Bits 2-0 - A Kind::* value indicating the kind of the operand. (KindField)
-  //   Bits 15-3 - The number of SDNode operands associated with
-  //               this inline assembly operand. (NumOperands)
-  //   Bit 31 - determines if this is a matched operand. (IsMatched)
+  //   Bits 2-0  - A Kind::* value indicating the kind of the operand.
+  //               (KindField)
+  //   Bits 15-3 - The number of SDNode operands associated with this inline
+  //               assembly operand. Once lowered to MIR, this represents the
+  //               number of MachineOperands necessary to refer to a
+  //               MachineOperandType::MO_FrameIndex. (NumOperands)
+  //   Bit 31    - Determines if this is a matched operand. (IsMatched)
   //   If bit 31 is set:
-  //     Bits 30-16 - The operand number that this operand must match. (MatchedOperandNo)
+  //     Bits 30-16 - The operand number that this operand must match.
+  //                  (MatchedOperandNo)
   //   Else if bits 2-0 are Kind::Mem:
-  //     Bits 30-16 - A ConstraintCode:: value indicating the original constraint code. (MemConstraintCode)
+  //     Bits 30-16 - A ConstraintCode:: value indicating the original
+  //                  constraint code. (MemConstraintCode)
   //   Else:
   //     Bits 30-16 - The register class ID to use for the operand. (RegClass)
   //

diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 55aece7edc9ca69..c0e88051dc427f1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5803,11 +5803,15 @@ TargetLowering::ConstraintWeight
 
 /// If there are multiple 
diff erent constraints that we could pick for this
 /// operand (e.g. "imr") try to pick the 'best' one.
-/// This is somewhat tricky: constraints fall into four classes:
-///    Other         -> immediates and magic values
+/// This is somewhat tricky: constraints (TargetLowering::ConstraintType) fall
+/// into seven classes:
 ///    Register      -> one specific register
 ///    RegisterClass -> a group of regs
 ///    Memory        -> memory
+///    Address       -> a symbolic memory reference
+///    Immediate     -> immediate values
+///    Other         -> magic values (such as "Flag Output Operands")
+///    Unknown       -> something we don't recognize yet and can't handle
 /// Ideally, we would pick the most specific constraint possible: if we have
 /// something that fits into a register, we would pick it.  The problem here
 /// is that if we have something that could either be in a register or in