[llvm] fb32baf - [ARM] Make some test checks more robust

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-09-28T14:26:13+01:00
New Revision: fb32baf0ec54005a13973201aacdcc03b1ffa9c1

URL: https://github.com/llvm/llvm-project/commit/fb32baf0ec54005a13973201aacdcc03b1ffa9c1
DIFF: https://github.com/llvm/llvm-project/commit/fb32baf0ec54005a13973201aacdcc03b1ffa9c1.diff

LOG: [ARM] Make some test checks more robust

This makes some tests robust against minor codegen differences
that will be caused by PR #67038.

Added: 
    

Modified: 
    llvm/test/CodeGen/ARM/atomic-64bit.ll
    llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/ARM/atomic-64bit.ll b/llvm/test/CodeGen/ARM/atomic-64bit.ll
index 312f9551573e127..ab9e1dfd1cfb19a 100644
--- a/llvm/test/CodeGen/ARM/atomic-64bit.ll
+++ b/llvm/test/CodeGen/ARM/atomic-64bit.ll
@@ -71,10 +71,10 @@ define i64 @test3(ptr %ptr, i64 %val) {
 ; CHECK-LABEL: test3:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
-; CHECK-LE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
+; CHECK-LE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]],
+; CHECK-LE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]],
+; CHECK-BE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]],
+; CHECK-BE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]],
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
@@ -83,10 +83,10 @@ define i64 @test3(ptr %ptr, i64 %val) {
 ; CHECK-THUMB-LABEL: test3:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]]
-; CHECK-THUMB-LE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]]
+; CHECK-THUMB-LE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]],
+; CHECK-THUMB-LE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]],
+; CHECK-THUMB-BE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]],
+; CHECK-THUMB-BE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]],
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
@@ -102,10 +102,10 @@ define i64 @test4(ptr %ptr, i64 %val) {
 ; CHECK-LABEL: test4:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
-; CHECK-LE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
+; CHECK-LE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]],
+; CHECK-LE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]],
+; CHECK-BE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]],
+; CHECK-BE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]],
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
@@ -114,10 +114,10 @@ define i64 @test4(ptr %ptr, i64 %val) {
 ; CHECK-THUMB-LABEL: test4:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
-; CHECK-THUMB-LE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
+; CHECK-THUMB-LE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]],
+; CHECK-THUMB-LE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]],
+; CHECK-THUMB-BE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]],
+; CHECK-THUMB-BE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]],
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
@@ -133,10 +133,10 @@ define i64 @test5(ptr %ptr, i64 %val) {
 ; CHECK-LABEL: test5:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
-; CHECK-LE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
+; CHECK-LE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]],
+; CHECK-LE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]],
+; CHECK-BE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]],
+; CHECK-BE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]],
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
@@ -145,10 +145,10 @@ define i64 @test5(ptr %ptr, i64 %val) {
 ; CHECK-THUMB-LABEL: test5:
 ; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
-; CHECK-THUMB-LE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
+; CHECK-THUMB-LE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]],
+; CHECK-THUMB-LE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]],
+; CHECK-THUMB-BE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]],
+; CHECK-THUMB-BE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]],
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne

diff  --git a/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll b/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll
index 40f9f0857a753ed..90fa45ecd5fe07c 100644
--- a/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll
+++ b/llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll
@@ -4,7 +4,7 @@
 ; register pressure and therefore spilling. There is more room for improvement
 ; here.
 
-; CHECK: sub sp, #{{40|36|32|28|24}}
+; CHECK: sub sp, #{{40|36|32|28|24|16}}
 
 ; CHECK: %for.inc
 ; CHECK-NOT: ldr