[llvm] cc62782 - Pre-commit some PowerPC test cases
Qiu Chaofan via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 28 00:52:05 PDT 2023
Author: Qiu Chaofan
Date: 2023-09-28T15:51:14+08:00
New Revision: cc627828f5176c6d75a25f1756d387d18539c1fb
URL: https://github.com/llvm/llvm-project/commit/cc627828f5176c6d75a25f1756d387d18539c1fb
DIFF: https://github.com/llvm/llvm-project/commit/cc627828f5176c6d75a25f1756d387d18539c1fb.diff
LOG: Pre-commit some PowerPC test cases
Added:
llvm/test/CodeGen/PowerPC/rldimi.ll
Modified:
llvm/test/CodeGen/PowerPC/fp-classify.ll
llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/fp-classify.ll b/llvm/test/CodeGen/PowerPC/fp-classify.ll
index 2079ca992629450..26cde62071224fb 100644
--- a/llvm/test/CodeGen/PowerPC/fp-classify.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-classify.ll
@@ -106,21 +106,141 @@ entry:
ret i1 %cmpinf
}
+define zeroext i1 @abs_isinfornanf(float %x) {
+; P8-LABEL: abs_isinfornanf:
+; P8: # %bb.0: # %entry
+; P8-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; P8-NEXT: xsabsdp 0, 1
+; P8-NEXT: lfs 1, .LCPI3_0 at toc@l(3)
+; P8-NEXT: li 3, 1
+; P8-NEXT: fcmpu 0, 0, 1
+; P8-NEXT: isellt 3, 0, 3
+; P8-NEXT: blr
+;
+; P9-LABEL: abs_isinfornanf:
+; P9: # %bb.0: # %entry
+; P9-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; P9-NEXT: xsabsdp 0, 1
+; P9-NEXT: lfs 1, .LCPI3_0 at toc@l(3)
+; P9-NEXT: li 3, 1
+; P9-NEXT: fcmpu 0, 0, 1
+; P9-NEXT: isellt 3, 0, 3
+; P9-NEXT: blr
+entry:
+ %0 = tail call float @llvm.fabs.f32(float %x)
+ %cmpinf = fcmp ueq float %0, 0x7FF0000000000000
+ ret i1 %cmpinf
+}
+
+define zeroext i1 @abs_isinfornan(double %x) {
+; P8-LABEL: abs_isinfornan:
+; P8: # %bb.0: # %entry
+; P8-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; P8-NEXT: xsabsdp 0, 1
+; P8-NEXT: lfs 1, .LCPI4_0 at toc@l(3)
+; P8-NEXT: li 3, 1
+; P8-NEXT: fcmpu 0, 0, 1
+; P8-NEXT: isellt 3, 0, 3
+; P8-NEXT: blr
+;
+; P9-LABEL: abs_isinfornan:
+; P9: # %bb.0: # %entry
+; P9-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; P9-NEXT: xsabsdp 0, 1
+; P9-NEXT: lfs 1, .LCPI4_0 at toc@l(3)
+; P9-NEXT: li 3, 1
+; P9-NEXT: fcmpu 0, 0, 1
+; P9-NEXT: isellt 3, 0, 3
+; P9-NEXT: blr
+entry:
+ %0 = tail call double @llvm.fabs.f64(double %x)
+ %cmpinf = fcmp ueq double %0, 0x7FF0000000000000
+ ret i1 %cmpinf
+}
+
+define zeroext i1 @abs_isinfornanq(fp128 %x) {
+; P8-LABEL: abs_isinfornanq:
+; P8: # %bb.0: # %entry
+; P8-NEXT: mflr 0
+; P8-NEXT: stdu 1, -112(1)
+; P8-NEXT: std 0, 128(1)
+; P8-NEXT: .cfi_def_cfa_offset 112
+; P8-NEXT: .cfi_offset lr, 16
+; P8-NEXT: .cfi_offset r30, -16
+; P8-NEXT: .cfi_offset v30, -48
+; P8-NEXT: .cfi_offset v31, -32
+; P8-NEXT: li 3, 64
+; P8-NEXT: xxswapd 0, 34
+; P8-NEXT: std 30, 96(1) # 8-byte Folded Spill
+; P8-NEXT: stvx 30, 1, 3 # 16-byte Folded Spill
+; P8-NEXT: li 3, 80
+; P8-NEXT: stvx 31, 1, 3 # 16-byte Folded Spill
+; P8-NEXT: addi 3, 1, 48
+; P8-NEXT: stxvd2x 0, 0, 3
+; P8-NEXT: lbz 4, 63(1)
+; P8-NEXT: clrlwi 4, 4, 25
+; P8-NEXT: stb 4, 63(1)
+; P8-NEXT: lxvd2x 0, 0, 3
+; P8-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
+; P8-NEXT: addi 3, 3, .LCPI5_0 at toc@l
+; P8-NEXT: xxswapd 63, 0
+; P8-NEXT: lxvd2x 0, 0, 3
+; P8-NEXT: vmr 2, 31
+; P8-NEXT: xxswapd 62, 0
+; P8-NEXT: vmr 3, 30
+; P8-NEXT: bl __eqkf2
+; P8-NEXT: nop
+; P8-NEXT: cntlzw 3, 3
+; P8-NEXT: vmr 2, 31
+; P8-NEXT: vmr 3, 30
+; P8-NEXT: srwi 30, 3, 5
+; P8-NEXT: bl __unordkf2
+; P8-NEXT: nop
+; P8-NEXT: cntlzw 3, 3
+; P8-NEXT: li 4, 80
+; P8-NEXT: lvx 31, 1, 4 # 16-byte Folded Reload
+; P8-NEXT: li 4, 64
+; P8-NEXT: srwi 3, 3, 5
+; P8-NEXT: lvx 30, 1, 4 # 16-byte Folded Reload
+; P8-NEXT: xori 3, 3, 1
+; P8-NEXT: or 3, 3, 30
+; P8-NEXT: ld 30, 96(1) # 8-byte Folded Reload
+; P8-NEXT: addi 1, 1, 112
+; P8-NEXT: ld 0, 16(1)
+; P8-NEXT: mtlr 0
+; P8-NEXT: blr
+;
+; P9-LABEL: abs_isinfornanq:
+; P9: # %bb.0: # %entry
+; P9-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
+; P9-NEXT: xsabsqp 2, 2
+; P9-NEXT: addi 3, 3, .LCPI5_0 at toc@l
+; P9-NEXT: lxv 35, 0(3)
+; P9-NEXT: li 3, 1
+; P9-NEXT: xscmpuqp 0, 2, 3
+; P9-NEXT: isellt 3, 0, 3
+; P9-NEXT: blr
+entry:
+ %0 = tail call fp128 @llvm.fabs.f128(fp128 %x)
+ %cmpinf = fcmp ueq fp128 %0, 0xL00000000000000007FFF000000000000
+ ret i1 %cmpinf
+}
+
define <4 x i1> @abs_isinfv4f32(<4 x float> %x) {
; P8-LABEL: abs_isinfv4f32:
; P8: # %bb.0: # %entry
-; P8-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; P8-NEXT: addis 3, 2, .LCPI6_0 at toc@ha
; P8-NEXT: xvabssp 0, 34
-; P8-NEXT: addi 3, 3, .LCPI3_0 at toc@l
+; P8-NEXT: addi 3, 3, .LCPI6_0 at toc@l
; P8-NEXT: lxvd2x 1, 0, 3
; P8-NEXT: xvcmpeqsp 34, 0, 1
; P8-NEXT: blr
;
; P9-LABEL: abs_isinfv4f32:
; P9: # %bb.0: # %entry
-; P9-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; P9-NEXT: addis 3, 2, .LCPI6_0 at toc@ha
; P9-NEXT: xvabssp 0, 34
-; P9-NEXT: addi 3, 3, .LCPI3_0 at toc@l
+; P9-NEXT: addi 3, 3, .LCPI6_0 at toc@l
; P9-NEXT: lxv 1, 0(3)
; P9-NEXT: xvcmpeqsp 34, 0, 1
; P9-NEXT: blr
@@ -133,18 +253,18 @@ entry:
define <2 x i1> @abs_isinfv2f64(<2 x double> %x) {
; P8-LABEL: abs_isinfv2f64:
; P8: # %bb.0: # %entry
-; P8-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; P8-NEXT: addis 3, 2, .LCPI7_0 at toc@ha
; P8-NEXT: xvabsdp 0, 34
-; P8-NEXT: addi 3, 3, .LCPI4_0 at toc@l
+; P8-NEXT: addi 3, 3, .LCPI7_0 at toc@l
; P8-NEXT: lxvd2x 1, 0, 3
; P8-NEXT: xvcmpeqdp 34, 0, 1
; P8-NEXT: blr
;
; P9-LABEL: abs_isinfv2f64:
; P9: # %bb.0: # %entry
-; P9-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; P9-NEXT: addis 3, 2, .LCPI7_0 at toc@ha
; P9-NEXT: xvabsdp 0, 34
-; P9-NEXT: addi 3, 3, .LCPI4_0 at toc@l
+; P9-NEXT: addi 3, 3, .LCPI7_0 at toc@l
; P9-NEXT: lxv 1, 0(3)
; P9-NEXT: xvcmpeqdp 34, 0, 1
; P9-NEXT: blr
@@ -208,8 +328,8 @@ define zeroext i1 @iszeroq(fp128 %x) {
; P8-NEXT: std 0, 48(1)
; P8-NEXT: .cfi_def_cfa_offset 32
; P8-NEXT: .cfi_offset lr, 16
-; P8-NEXT: addis 3, 2, .LCPI7_0 at toc@ha
-; P8-NEXT: addi 3, 3, .LCPI7_0 at toc@l
+; P8-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
+; P8-NEXT: addi 3, 3, .LCPI10_0 at toc@l
; P8-NEXT: lxvd2x 0, 0, 3
; P8-NEXT: xxswapd 35, 0
; P8-NEXT: bl __eqkf2
@@ -223,9 +343,9 @@ define zeroext i1 @iszeroq(fp128 %x) {
;
; P9-LABEL: iszeroq:
; P9: # %bb.0: # %entry
-; P9-NEXT: addis 3, 2, .LCPI7_0 at toc@ha
+; P9-NEXT: addis 3, 2, .LCPI10_0 at toc@ha
; P9-NEXT: li 4, 1
-; P9-NEXT: addi 3, 3, .LCPI7_0 at toc@l
+; P9-NEXT: addi 3, 3, .LCPI10_0 at toc@l
; P9-NEXT: lxv 35, 0(3)
; P9-NEXT: li 3, 0
; P9-NEXT: xscmpuqp 0, 2, 3
diff --git a/llvm/test/CodeGen/PowerPC/rldimi.ll b/llvm/test/CodeGen/PowerPC/rldimi.ll
new file mode 100644
index 000000000000000..4e26ddfc37f99e3
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/rldimi.ll
@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix -mcpu=pwr8 | FileCheck %s
+
+define i64 @rldimi1(i64 %a) {
+; CHECK-LABEL: rldimi1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rldimi 3, 3, 8, 0
+; CHECK-NEXT: blr
+entry:
+ %x0 = shl i64 %a, 8
+ %x1 = and i64 %a, 255
+ %x2 = or i64 %x0, %x1
+ ret i64 %x2
+}
+
+define i64 @rldimi2(i64 %a) {
+; CHECK-LABEL: rldimi2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mr 4, 3
+; CHECK-NEXT: rlwimi 4, 3, 8, 16, 23
+; CHECK-NEXT: rlwimi 4, 3, 16, 8, 15
+; CHECK-NEXT: rldimi 4, 3, 24, 0
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: blr
+entry:
+ %x0 = shl i64 %a, 8
+ %x1 = and i64 %a, 255
+ %x2 = or i64 %x0, %x1
+ %x3 = shl i64 %x2, 16
+ %x4 = and i64 %x2, 65535
+ %x5 = or i64 %x3, %x4
+ ret i64 %x5
+}
+
+define i64 @rldimi3(i64 %a) {
+; CHECK-LABEL: rldimi3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rotldi 4, 3, 32
+; CHECK-NEXT: rlwimi 4, 3, 0, 24, 31
+; CHECK-NEXT: rlwimi 4, 3, 8, 16, 23
+; CHECK-NEXT: rlwimi 4, 3, 16, 8, 15
+; CHECK-NEXT: rlwimi 4, 3, 24, 0, 7
+; CHECK-NEXT: rldimi 4, 3, 40, 16
+; CHECK-NEXT: rldimi 4, 3, 48, 8
+; CHECK-NEXT: rldimi 4, 3, 56, 0
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: blr
+entry:
+ %0 = shl i64 %a, 8
+ %1 = and i64 %a, 255
+ %2 = or i64 %0, %1
+ %3 = shl i64 %2, 16
+ %4 = and i64 %2, 65535
+ %5 = or i64 %3, %4
+ %6 = shl i64 %5, 32
+ %7 = and i64 %5, 4294967295
+ %8 = or i64 %6, %7
+ ret i64 %8
+}
diff --git a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
index 13c629b6349450c..20dcb8ccf4908a9 100644
--- a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
@@ -89,6 +89,101 @@ entry:
ret i1 %cmp.i5
}
+define zeroext i1 @test5(i64 %a) {
+; CHECK-LABEL: test5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li 4, -1
+; CHECK-NEXT: addis 3, 3, -32768
+; CHECK-NEXT: rldic 4, 4, 32, 0
+; CHECK-NEXT: subc 4, 3, 4
+; CHECK-NEXT: subfe 3, 3, 3
+; CHECK-NEXT: neg 3, 3
+; CHECK-NEXT: blr
+entry:
+ %0 = add i64 %a, -2147483648
+ %cmp = icmp ult i64 %0, -4294967296
+ ret i1 %cmp
+}
+
+define zeroext i1 @test6(i64 %a) {
+; CHECK-LABEL: test6:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi 3, 3, -32768
+; CHECK-NEXT: lis 4, -1
+; CHECK-NEXT: subc 4, 3, 4
+; CHECK-NEXT: subfe 3, 3, 3
+; CHECK-NEXT: neg 3, 3
+; CHECK-NEXT: blr
+entry:
+ %0 = add i64 %a, -32768
+ %cmp = icmp ult i64 %0, -65536
+ ret i1 %cmp
+}
+
+define zeroext i1 @test7(i64 %a) {
+; CHECK-LABEL: test7:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi 3, 3, -128
+; CHECK-NEXT: li 4, -256
+; CHECK-NEXT: subc 4, 3, 4
+; CHECK-NEXT: subfe 3, 3, 3
+; CHECK-NEXT: neg 3, 3
+; CHECK-NEXT: blr
+entry:
+ %0 = add i64 %a, -128
+ %cmp = icmp ult i64 %0, -256
+ ret i1 %cmp
+}
+
+define zeroext i1 @test8(i32 %a) {
+; CHECK-LABEL: test8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi 3, 3, -32768
+; CHECK-NEXT: lis 4, -1
+; CHECK-NEXT: rlwinm 3, 3, 16, 16, 31
+; CHECK-NEXT: ori 4, 4, 1
+; CHECK-NEXT: add 3, 3, 4
+; CHECK-NEXT: rldicl 3, 3, 1, 63
+; CHECK-NEXT: blr
+entry:
+ %0 = add i32 %a, -32768
+ %cmp = icmp ult i32 %0, -65536
+ ret i1 %cmp
+}
+
+define zeroext i1 @test9(i32 %a) {
+; CHECK-LABEL: test9:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lis 4, -256
+; CHECK-NEXT: addi 3, 3, -128
+; CHECK-NEXT: ori 4, 4, 1
+; CHECK-NEXT: clrldi 3, 3, 32
+; CHECK-NEXT: rldic 4, 4, 8, 0
+; CHECK-NEXT: add 3, 3, 4
+; CHECK-NEXT: rldicl 3, 3, 1, 63
+; CHECK-NEXT: blr
+entry:
+ %0 = add i32 %a, -128
+ %cmp = icmp ult i32 %0, -256
+ ret i1 %cmp
+}
+
+define zeroext i1 @test10(i16 %a) {
+; CHECK-LABEL: test10:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi 3, 3, -128
+; CHECK-NEXT: lis 4, -1
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: ori 4, 4, 256
+; CHECK-NEXT: add 3, 3, 4
+; CHECK-NEXT: rldicl 3, 3, 1, 63
+; CHECK-NEXT: blr
+entry:
+ %0 = add i16 %a, -128
+ %cmp = icmp ult i16 %0, -256
+ ret i1 %cmp
+}
+
!1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
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