[llvm] [AArch64][SME] Use PNR Reg classes for predicate constraint (PR #67606)

[Sander de Smalen via llvm-commits]

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@@ -10052,18 +10052,21 @@ static PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
 
 static const TargetRegisterClass *
 getPredicateRegisterClass(PredicateConstraint Constraint, EVT VT) {
-  if (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1)
+  if (VT != MVT::aarch64svcount &&
+      (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1))
     return nullptr;
 
   switch (Constraint) {
   default:
     return nullptr;
   case PredicateConstraint::Uph:
-    return &AArch64::PPR_p8to15RegClass;
+    return VT == MVT::aarch64svcount ? &AArch64::PNR_p8to15RegClass
+                                     : &AArch64::PPR_p8to15RegClass;
   case PredicateConstraint::Upl:
-    return &AArch64::PPR_3bRegClass;
+    return VT == MVT::aarch64svcount ? nullptr : &AArch64::PPR_3bRegClass;
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sdesmalen-arm wrote:

We should probably add a PNR_3bRegClass as well, even if this isn't used by any of the instructions, but at least it will allow users to limit the chosen register to pn0-pn7. Could you add it? (I'm happy for this to be done in a separate patch if this leads to those flaky tests needing to be updated)

https://github.com/llvm/llvm-project/pull/67606