[llvm] 9d48856 - [RISCV][GISel] Remove source constraint from selectCopy and use it fo… (#67207)

[via llvm-commits]

Author: Craig Topper
Date: 2023-09-27T15:06:30-07:00
New Revision: 9d488569bbc44ae21a9ae31f77750f7fa6f4d3ad

URL: https://github.com/llvm/llvm-project/commit/9d488569bbc44ae21a9ae31f77750f7fa6f4d3ad
DIFF: https://github.com/llvm/llvm-project/commit/9d488569bbc44ae21a9ae31f77750f7fa6f4d3ad.diff

LOG: [RISCV][GISel] Remove source constraint from selectCopy and use it fo… (#67207)

…r G_ANYEXT/G_TRUNC.

AArch64, Mips, and ARM do not have source constraints in their version
of selectCopy. I'm assuming we don't need it either.

We weren't constraining the destination register of G_ANYEXT/G_TRUNC
previously, but we got away with it in our tests because all their users
constrained them as a use. When I removed the source constraint from
selectCopy this stopped working.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 2e690a3624edcb3..4f97a0d84f686f9 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -226,8 +226,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   switch (Opc) {
   case TargetOpcode::G_ANYEXT:
   case TargetOpcode::G_TRUNC:
-    MI.setDesc(TII.get(TargetOpcode::COPY));
-    return true;
+    return selectCopy(MI, MRI);
   case TargetOpcode::G_CONSTANT:
     return selectConstant(MI, MIB, MRI);
   case TargetOpcode::G_BRCOND: {
@@ -268,37 +267,25 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
 bool RISCVInstructionSelector::selectCopy(MachineInstr &MI,
                                           MachineRegisterInfo &MRI) const {
   Register DstReg = MI.getOperand(0).getReg();
-  Register SrcReg = MI.getOperand(1).getReg();
 
-  if (Register::isPhysicalRegister(SrcReg) &&
-      Register::isPhysicalRegister(DstReg))
+  if (DstReg.isPhysical())
     return true;
 
-  if (!Register::isPhysicalRegister(SrcReg)) {
-    const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(
-        MRI.getType(SrcReg), *RBI.getRegBank(SrcReg, MRI, TRI));
-    assert(SrcRC &&
-           "Register class not available for LLT, register bank combination");
-
-    if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI)) {
-      LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode())
-                        << " operand\n");
-      return false;
-    }
-  }
-  if (!Register::isPhysicalRegister(DstReg)) {
-    const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(
-        MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI));
-    assert(DstRC &&
-           "Register class not available for LLT, register bank combination");
-
-    if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
-      LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode())
-                        << " operand\n");
-      return false;
-    }
+  const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(
+      MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI));
+  assert(DstRC &&
+         "Register class not available for LLT, register bank combination");
+
+  // No need to constrain SrcReg. It will get constrained when
+  // we hit another of its uses or its defs.
+  // Copies do not have constraints.
+  if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
+    LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode())
+                      << " operand\n");
+    return false;
   }
 
+  MI.setDesc(TII.get(RISCV::COPY));
   return true;
 }