[llvm] [RISCV][WIP] Enable sink-and-fold for RISC-V. (PR #67602)

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git-clang-format --diff d87f9e287217053bd4613e025c3fb0a941fd0196 fc922af83f8debc37f55bfb7d96d23ff740f89a1 -- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 7b9f8b08002c..244e80c6ad36 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1907,8 +1907,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
   return true;
 }
 
-bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI,
-                                         Register Reg,
+bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
                                          const MachineInstr &AddrI,
                                          ExtAddrMode &AM) const {
   switch (MemI.getOpcode()) {
@@ -1969,13 +1968,13 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
          "Addressing mode not supported for folding");
 
   auto B = BuildMI(MBB, MemI, DL, get(MemI.getOpcode()))
-                 .addReg(MemI.getOperand(0).getReg(),
-                         MemI.mayLoad() ? RegState::Define : 0)
-                 .addReg(AM.BaseReg)
-                 .addImm(AM.Displacement)
-                 .setMemRefs(MemI.memoperands())
-                 .setMIFlags(MemI.getFlags());
-    return B.getInstr();
+               .addReg(MemI.getOperand(0).getReg(),
+                       MemI.mayLoad() ? RegState::Define : 0)
+               .addReg(AM.BaseReg)
+               .addImm(AM.Displacement)
+               .setMemRefs(MemI.memoperands())
+               .setMIFlags(MemI.getFlags());
+  return B.getInstr();
 }
 
 // Return true if get the base operand, byte offset of an instruction and the

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https://github.com/llvm/llvm-project/pull/67602