[llvm] 8e6db7e - [RISCV] Fix a crash from trying to truncate an FP type in lowerBuildV… (#67488)

[via llvm-commits]

Author: Craig Topper
Date: 2023-09-27T12:21:10-07:00
New Revision: 8e6db7e2b2b4c4cbd13a8f5177358118e12d40d4

URL: https://github.com/llvm/llvm-project/commit/8e6db7e2b2b4c4cbd13a8f5177358118e12d40d4
DIFF: https://github.com/llvm/llvm-project/commit/8e6db7e2b2b4c4cbd13a8f5177358118e12d40d4.diff

LOG: [RISCV] Fix a crash from trying to truncate an FP type in lowerBuildV… (#67488)

…ectorOfConstants.

ComputeNumSignBits can return an answer for FP constants based on
bitcasting them to int.

Check for an integer type so we don't create an illegal truncate.

We could support this case with bitcasts, but I leave that to a separate
patch.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2b8e5aeeb86405a..e018d1b5e6e442d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3526,7 +3526,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
   // narrow vector is known to materialize cheaply.
   // TODO: We really should be costing the smaller vector.  There are
   // profitable cases this misses.
-  if (EltBitSize > 8 &&
+  if (EltBitSize > 8 && VT.isInteger() &&
       (NumElts <= 4 || VT.getSizeInBits() > Subtarget.getRealMinVLen())) {
     unsigned SignBits = DAG.ComputeNumSignBits(Op);
     if (EltBitSize - SignBits < 8) {

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index a2fde2addc14e66..7593c1ab75ce420 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -1076,3 +1076,10 @@ define <32 x double> @buildvec_v32f64(double %e0, double %e1, double %e2, double
   %v31 = insertelement <32 x double> %v30, double %e31, i64 31
   ret <32 x double> %v31
 }
+
+; FIXME: These constants have enough sign bits that we could use vmv.v.x/i and
+; vsext, but we don't support this for FP yet.
+define <2 x float> @signbits() {
+entry:
+  ret <2 x float> <float 0x36A0000000000000, float 0.000000e+00>
+}