[llvm] Add option -enable-machine-licm (PR #67589)
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Wed Sep 27 11:58:34 PDT 2023
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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You can test this locally with the following command:
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``````````bash
git-clang-format --diff 5ffbdd9ed5fb719b354e4a46acc8737c5b624f94 76f92c66e8a32e476ca134066a24b5e1a741f7ea -- llvm/lib/CodeGen/MachineLICM.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index a66e80e11..9097bcf9d 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -58,10 +58,9 @@ using namespace llvm;
#define DEBUG_TYPE "machinelicm"
-static cl::opt<bool>
-EnableMachineLICM("enable-machine-licm",
- cl::desc("Enable MachineLICM"),
- cl::init(true), cl::Hidden);
+static cl::opt<bool> EnableMachineLICM("enable-machine-licm",
+ cl::desc("Enable MachineLICM"),
+ cl::init(true), cl::Hidden);
static cl::opt<bool>
AvoidSpeculation("avoid-speculation",
@@ -335,35 +334,35 @@ INITIALIZE_PASS_END(EarlyMachineLICM, "early-machinelicm",
"Early Machine Loop Invariant Code Motion", false, false)
bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
- if (!EnableMachineLICM || skipFunction(MF.getFunction()))
- return false;
+ if (!EnableMachineLICM || skipFunction(MF.getFunction()))
+ return false;
- Changed = FirstInLoop = false;
- const TargetSubtargetInfo &ST = MF.getSubtarget();
- TII = ST.getInstrInfo();
- TLI = ST.getTargetLowering();
- TRI = ST.getRegisterInfo();
- MFI = &MF.getFrameInfo();
- MRI = &MF.getRegInfo();
- SchedModel.init(&ST);
-
- PreRegAlloc = MRI->isSSA();
- HasProfileData = MF.getFunction().hasProfileData();
-
- if (PreRegAlloc)
- LLVM_DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
- else
- LLVM_DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
- LLVM_DEBUG(dbgs() << MF.getName() << " ********\n");
-
- if (PreRegAlloc) {
- // Estimate register pressure during pre-regalloc pass.
- unsigned NumRPS = TRI->getNumRegPressureSets();
- RegPressure.resize(NumRPS);
- std::fill(RegPressure.begin(), RegPressure.end(), 0);
- RegLimit.resize(NumRPS);
- for (unsigned i = 0, e = NumRPS; i != e; ++i)
- RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
+ Changed = FirstInLoop = false;
+ const TargetSubtargetInfo &ST = MF.getSubtarget();
+ TII = ST.getInstrInfo();
+ TLI = ST.getTargetLowering();
+ TRI = ST.getRegisterInfo();
+ MFI = &MF.getFrameInfo();
+ MRI = &MF.getRegInfo();
+ SchedModel.init(&ST);
+
+ PreRegAlloc = MRI->isSSA();
+ HasProfileData = MF.getFunction().hasProfileData();
+
+ if (PreRegAlloc)
+ LLVM_DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
+ else
+ LLVM_DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
+ LLVM_DEBUG(dbgs() << MF.getName() << " ********\n");
+
+ if (PreRegAlloc) {
+ // Estimate register pressure during pre-regalloc pass.
+ unsigned NumRPS = TRI->getNumRegPressureSets();
+ RegPressure.resize(NumRPS);
+ std::fill(RegPressure.begin(), RegPressure.end(), 0);
+ RegLimit.resize(NumRPS);
+ for (unsigned i = 0, e = NumRPS; i != e; ++i)
+ RegLimit[i] = TRI->getRegPressureSetLimit(MF, i);
}
// Get our Loop information...
``````````
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https://github.com/llvm/llvm-project/pull/67589
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