[llvm] [BOLT][RISCV] Implement R_RISCV_64 (PR #67558)

[Job Noorman via llvm-commits]

https://github.com/mtvec created https://github.com/llvm/llvm-project/pull/67558

Relocation for 64-bit absolute values.

Note that this patch also implements two `Relocation` methods (`encodeValue` and `getAbs64`) that will become necessary to support instrumentation of non-PIE binaries (see #67348). However, I didn't find a way to test those independent of instrumentation.

>From a55064afd4b7523c9ef785117bfb6783e19d9d77 Mon Sep 17 00:00:00 2001
From: Job Noorman <jnoorman at igalia.com>
Date: Wed, 27 Sep 2023 15:00:46 +0200
Subject: [PATCH] [BOLT][RISCV] Implement R_RISCV_64

Relocation for 64-bit absolute values.

Note that this patch also implements two `Relocation` methods
(`encodeValue` and `getAbs64`) that will become necessary to support
instrumentation of non-PIE binaries (see #67348). However, I didn't find
a way to test those independent of instrumentation.
---
 bolt/lib/Core/Relocation.cpp | 18 +++++++++++++++++-
 bolt/test/RISCV/reloc-64.s   | 26 ++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100644 bolt/test/RISCV/reloc-64.s

diff --git a/bolt/lib/Core/Relocation.cpp b/bolt/lib/Core/Relocation.cpp
index ff539b4667d503a..a73545905c545f4 100644
--- a/bolt/lib/Core/Relocation.cpp
+++ b/bolt/lib/Core/Relocation.cpp
@@ -109,6 +109,7 @@ static bool isSupportedRISCV(uint64_t Type) {
   case ELF::R_RISCV_HI20:
   case ELF::R_RISCV_LO12_I:
   case ELF::R_RISCV_LO12_S:
+  case ELF::R_RISCV_64:
     return true;
   }
 }
@@ -209,6 +210,7 @@ static size_t getSizeForTypeRISCV(uint64_t Type) {
   case ELF::R_RISCV_LO12_I:
   case ELF::R_RISCV_LO12_S:
     return 4;
+  case ELF::R_RISCV_64:
   case ELF::R_RISCV_GOT_HI20:
     // See extractValueRISCV for why this is necessary.
     return 8;
@@ -364,6 +366,16 @@ static uint64_t encodeValueAArch64(uint64_t Type, uint64_t Value, uint64_t PC) {
   return Value;
 }
 
+static uint64_t encodeValueRISCV(uint64_t Type, uint64_t Value, uint64_t PC) {
+  switch (Type) {
+  default:
+    llvm_unreachable("unsupported relocation");
+  case ELF::R_RISCV_64:
+    break;
+  }
+  return Value;
+}
+
 static uint64_t extractValueX86(uint64_t Type, uint64_t Contents, uint64_t PC) {
   if (Type == ELF::R_X86_64_32S)
     return SignExtend64<32>(Contents);
@@ -539,6 +551,7 @@ static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents,
     return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0));
   case ELF::R_RISCV_ADD32:
   case ELF::R_RISCV_SUB32:
+  case ELF::R_RISCV_64:
     return Contents;
   }
 }
@@ -704,6 +717,7 @@ static bool isPCRelativeRISCV(uint64_t Type) {
   case ELF::R_RISCV_HI20:
   case ELF::R_RISCV_LO12_I:
   case ELF::R_RISCV_LO12_S:
+  case ELF::R_RISCV_64:
     return false;
   case ELF::R_RISCV_JAL:
   case ELF::R_RISCV_CALL:
@@ -756,7 +770,7 @@ uint64_t Relocation::encodeValue(uint64_t Type, uint64_t Value, uint64_t PC) {
   if (Arch == Triple::aarch64)
     return encodeValueAArch64(Type, Value, PC);
   if (Arch == Triple::riscv64)
-    llvm_unreachable("not implemented");
+    return encodeValueRISCV(Type, Value, PC);
   return encodeValueX86(Type, Value, PC);
 }
 
@@ -844,6 +858,8 @@ bool Relocation::isPCRelative(uint64_t Type) {
 uint64_t Relocation::getAbs64() {
   if (Arch == Triple::aarch64)
     return ELF::R_AARCH64_ABS64;
+  if (Arch == Triple::riscv64)
+    return ELF::R_RISCV_64;
   return ELF::R_X86_64_64;
 }
 
diff --git a/bolt/test/RISCV/reloc-64.s b/bolt/test/RISCV/reloc-64.s
new file mode 100644
index 000000000000000..a08d4a72ad0bef4
--- /dev/null
+++ b/bolt/test/RISCV/reloc-64.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple riscv64 -filetype=obj -o %t.o %s
+// RUN: ld.lld -q -o %t %t.o
+// RUN: llvm-bolt -o %t.bolt %t
+// RUN: llvm-readelf -s %t.bolt | FileCheck --check-prefix=SYM %s
+// RUN: llvm-readelf -x .data %t.bolt | FileCheck --check-prefix=DATA %s
+
+// SYM: {{0+}}400000 {{.*}} _start{{$}}
+
+// DATA: Hex dump of section '.data':
+// DATA-NEXT: 00004000 00000000
+
+  .data
+  .globl d
+  .p2align 3
+d:
+  .dword _start
+
+  .text
+  .globl _start
+  .p2align 1
+_start:
+  ret
+  ## Dummy relocation to force relocation mode; without it, _start will not be
+  ## moved to a new address.
+  .reloc 0, R_RISCV_NONE
+  .size _start, .-_start